-------------------------------------------------------- -- BSDL for ADSP-2126x Digital Signal Processor -- 144 pin LQFP Package -- -- Revision 1.1 29-Oct-2004 -- -- 1) Changed the port definition from "out" to "inout" for: -- "RD_B, WR_B, ALE, CLKOUT, EMU_B" pins -- 2) Replaced generic (PHYSICAL_PIN_MAP : string:="UNDEFINED"); -- with generic (PHYSICAL_PIN_MAP : string:="BGA_PACKAGE"); -- 3) Changed ordering of AD, DAIP pins -- -- -- Revision 1.0 -- Initial Release -- -------------------------------------------------------- entity ADSP_2126x is generic (PHYSICAL_PIN_MAP : string:="QFP_PACKAGE"); port( AD: inout bit_vector(0 to 15); DAIP: inout bit_vector(1 to 20); RD_B: inout bit; WR_B: inout bit; ALE: inout bit; FLAG0: inout bit; FLAG1: inout bit; FLAG2: inout bit; FLAG3: inout bit; SPICLK: inout bit; SPIDS_B: in bit; MOSI: inout bit; MISO: inout bit; CLKIN: linkage bit; XTAL: linkage bit; CLKOUT: inout bit; CLKCFG0: in bit; CLKCFG1: in bit; BOOTCFG0: in bit; BOOTCFG1: in bit; RESET_B: in bit; TCK: in bit; TMS: in bit; TDI: in bit; TDO: out bit; TRST_B: in bit; EMU_B: inout bit; AVDD: linkage bit; AVSS: linkage bit; IOVDD: linkage bit_vector(0 to 9); VDD: linkage bit_vector(0 to 31); GND: linkage bit_vector(0 to 38)); use STD_1149_1_1990.all; attribute PIN_MAP of ADSP_2126x: entity is PHYSICAL_PIN_MAP; constant QFP_PACKAGE: PIN_MAP_STRING:= "AD: (34,33,30,29,26,25,24,17," & "52,51,50,49,46,43,42,41)," & "DAIP: (53,56,57,62,63,64,65,70,71,77," & "78,79,80,81,82,86,87,88,89,94)," & "RD_B: 39," & "WR_B: 35," & "ALE: 40," & "FLAG0: 15," & "FLAG1: 16," & "FLAG2: 97," & "FLAG3: 98," & "SPICLK: 125," & "SPIDS_B: 122," & "MOSI: 127," & "MISO: 126," & "CLKIN: 142," & "XTAL: 143," & "CLKOUT: 134," & "CLKCFG0: 2," & "CLKCFG1: 3," & "BOOTCFG0: 4," & "BOOTCFG1: 5," & "RESET_B: 121," & "TCK: 139," & "TMS: 140," & "TDI: 137," & "TDO: 136," & "TRST_B: 138," & "EMU_B: 135," & "AVDD: 131," & "AVSS: 132," & "IOVDD: (7,21,31,45,59,73,93,116,130,144)," & "VDD: (1,9,11,13,19,23,27,36,37,47,54,60," & "66,68,72,75,83,90,96,99,101,103,105," & "107,108,110,112,114,118,120,124,129)," & "GND: (6,8,10,12,14,18,20,22,28,32,38,44,48," & "55,58,61,67,69,74,76,84,85,91,92,95," & "100,102,104,106,109,111,113,115,117," & "119,123,128,133,141)" ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST_B : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH); attribute INSTRUCTION_LENGTH of ADSP_2126x: entity is 5; -- Unspecified opcodes assigned to Bypass. attribute INSTRUCTION_OPCODE of ADSP_2126x: entity is "BYPASS (11111)," & "EXTEST (00000)," & "SAMPLE (10000)," & "INTEST (11000)," & "MEMTEST (10101)," & "EMULATION (00100,10100,10110,01100,11100,00010)"; attribute INSTRUCTION_CAPTURE of ADSP_2126x: entity is "00001"; attribute INSTRUCTION_PRIVATE of ADSP_2126x: entity is "EMULATION," & "MEMTEST"; -- attribute INSTRUCTION_USAGE of ADSP_2126x: entity is -- "INTEST (clock CLKIN)"; attribute BOUNDARY_CELLS of ADSP_2126x: entity is "BC_1, BC_2, BC_3, BC_4"; -- BC_1: output, control; BC_2: input; BC_3: internal; BC_4: clock; attribute BOUNDARY_LENGTH of ADSP_2126x: entity is 163; attribute BOUNDARY_REGISTER of ADSP_2126x: entity is --num cell port function safe [ccell disval rslt ] " 0 ( BC_3 , * , internal , X ) , " & " 1 ( BC_3 , * , internal , X ) , " & " 2 ( BC_2 , CLKCFG0 , input , X ) , " & " 3 ( BC_3 , * , internal , X ) , " & " 4 ( BC_3 , * , internal , X ) , " & " 5 ( BC_2 , CLKCFG1 , input , X ) , " & " 6 ( BC_3 , * , internal , X ) , " & " 7 ( BC_3 , * , internal , X ) , " & " 8 ( BC_2 , BOOTCFG0 , input , X ) , " & " 9 ( BC_3 , * , internal , X ) , " & " 10 ( BC_3 , * , internal , X ) , " & " 11 ( BC_2 , BOOTCFG1 , input , X ) , " & " 12 ( BC_1 , FLAG0 , output3 , X , 13 , 0 , Z ) , " & " 13 ( BC_1 , * , control , 0 ) , " & " 14 ( BC_2 , FLAG0 , input , X ) , " & " 15 ( BC_1 , FLAG1 , output3 , X , 16 , 0 , Z ) , " & " 16 ( BC_1 , * , control , 0 ) , " & " 17 ( BC_2 , FLAG1 , input , X ) , " & " 18 ( BC_1 , AD(7) , output3 , X , 19 , 0 , Z ) , " & " 19 ( BC_1 , * , control , 0 ) , " & " 20 ( BC_2 , AD(7) , input , X ) , " & " 21 ( BC_1 , AD(6) , output3 , X , 22 , 0 , Z ) , " & " 22 ( BC_1 , * , control , 0 ) , " & " 23 ( BC_2 , AD(6) , input , X ) , " & " 24 ( BC_1 , AD(5) , output3 , X , 25 , 0 , Z ) , " & " 25 ( BC_1 , * , control , 0 ) , " & " 26 ( BC_2 , AD(5) , input , X ) , " & " 27 ( BC_1 , AD(4) , output3 , X , 28 , 0 , Z ) , " & " 28 ( BC_1 , * , control , 0 ) , " & " 29 ( BC_2 , AD(4) , input , X ) , " & " 30 ( BC_1 , AD(3) , output3 , X , 31 , 0 , Z ) , " & " 31 ( BC_1 , * , control , 0 ) , " & " 32 ( BC_2 , AD(3) , input , X ) , " & " 33 ( BC_1 , AD(2) , output3 , X , 34 , 0 , Z ) , " & " 34 ( BC_1 , * , control , 0 ) , " & " 35 ( BC_2 , AD(2) , input , X ) , " & " 36 ( BC_1 , AD(1) , output3 , X , 37 , 0 , Z ) , " & " 37 ( BC_1 , * , control , 0 ) , " & " 38 ( BC_2 , AD(1) , input , X ) , " & " 39 ( BC_1 , AD(0) , output3 , X , 40 , 0 , Z ) , " & " 40 ( BC_1 , * , control , 0 ) , " & " 41 ( BC_2 , AD(0) , input , X ) , " & " 42 ( BC_1 , WR_B , output3 , X , 43 , 0 , Z ) , " & " 43 ( BC_1 , * , control , 0 ) , " & " 44 ( BC_2 , WR_B , input , X ) , " & " 45 ( BC_1 , RD_B , output3 , X , 46 , 0 , Z ) , " & " 46 ( BC_1 , * , control , 0 ) , " & " 47 ( BC_2 , RD_B , input , X ) , " & " 48 ( BC_1 , ALE , output3 , X , 49 , 0 , Z ) , " & " 49 ( BC_1 , * , control , 0 ) , " & " 50 ( BC_2 , ALE , input , X ) , " & " 51 ( BC_1 , AD(15) , output3 , X , 52 , 0 , Z ) , " & " 52 ( BC_1 , * , control , 0 ) , " & " 53 ( BC_2 , AD(15) , input , X ) , " & " 54 ( BC_1 , AD(14) , output3 , X , 55 , 0 , Z ) , " & " 55 ( BC_1 , * , control , 0 ) , " & " 56 ( BC_2 , AD(14) , input , X ) , " & " 57 ( BC_1 , AD(13) , output3 , X , 58 , 0 , Z ) , " & " 58 ( BC_1 , * , control , 0 ) , " & " 59 ( BC_2 , AD(13) , input , X ) , " & " 60 ( BC_1 , AD(12) , output3 , X , 61 , 0 , Z ) , " & " 61 ( BC_1 , * , control , 0 ) , " & " 62 ( BC_2 , AD(12) , input , X ) , " & " 63 ( BC_1 , AD(11) , output3 , X , 64 , 0 , Z ) , " & " 64 ( BC_1 , * , control , 0 ) , " & " 65 ( BC_2 , AD(11) , input , X ) , " & " 66 ( BC_1 , AD(10) , output3 , X , 67 , 0 , Z ) , " & " 67 ( BC_1 , * , control , 0 ) , " & " 68 ( BC_2 , AD(10) , input , X ) , " & " 69 ( BC_1 , AD(9) , output3 , X , 70 , 0 , Z ) , " & " 70 ( BC_1 , * , control , 0 ) , " & " 71 ( BC_2 , AD(9) , input , X ) , " & " 72 ( BC_1 , AD(8) , output3 , X , 73 , 0 , Z ) , " & " 73 ( BC_1 , * , control , 0 ) , " & " 74 ( BC_2 , AD(8) , input , X ) , " & " 75 ( BC_1 , DAIP(1) , output3 , X , 76 , 0 , Z ) , " & " 76 ( BC_1 , * , control , 0 ) , " & " 77 ( BC_2 , DAIP(1) , input , X ) , " & " 78 ( BC_1 , DAIP(2) , output3 , X , 79 , 0 , Z ) , " & " 79 ( BC_1 , * , control , 0 ) , " & " 80 ( BC_2 , DAIP(2) , input , X ) , " & " 81 ( BC_1 , DAIP(3) , output3 , X , 82 , 0 , Z ) , " & " 82 ( BC_1 , * , control , 0 ) , " & " 83 ( BC_2 , DAIP(3) , input , X ) , " & " 84 ( BC_1 , DAIP(4) , output3 , X , 85 , 0 , Z ) , " & " 85 ( BC_1 , * , control , 0 ) , " & " 86 ( BC_2 , DAIP(4) , input , X ) , " & " 87 ( BC_1 , DAIP(5) , output3 , X , 88 , 0 , Z ) , " & " 88 ( BC_1 , * , control , 0 ) , " & " 89 ( BC_2 , DAIP(5) , input , X ) , " & " 90 ( BC_1 , DAIP(6) , output3 , X , 91 , 0 , Z ) , " & " 91 ( BC_1 , * , control , 0 ) , " & " 92 ( BC_2 , DAIP(6) , input , X ) , " & " 93 ( BC_1 , DAIP(7) , output3 , X , 94 , 0 , Z ) , " & " 94 ( BC_1 , * , control , 0 ) , " & " 95 ( BC_2 , DAIP(7) , input , X ) , " & " 96 ( BC_1 , DAIP(8) , output3 , X , 97 , 0 , Z ) , " & " 97 ( BC_1 , * , control , 0 ) , " & " 98 ( BC_2 , DAIP(8) , input , X ) , " & " 99 ( BC_1 , DAIP(9) , output3 , X , 100 , 0 , Z ) , " & " 100 ( BC_1 , * , control , 0 ) , " & " 101 ( BC_2 , DAIP(9) , input , X ) , " & " 102 ( BC_1 , DAIP(10) , output3 , X , 103 , 0 , Z ) , " & " 103 ( BC_1 , * , control , 0 ) , " & " 104 ( BC_2 , DAIP(10) , input , X ) , " & " 105 ( BC_1 , DAIP(11) , output3 , X , 106 , 0 , Z ) , " & " 106 ( BC_1 , * , control , 0 ) , " & " 107 ( BC_2 , DAIP(11) , input , X ) , " & " 108 ( BC_1 , DAIP(12) , output3 , X , 109 , 0 , Z ) , " & " 109 ( BC_1 , * , control , 0 ) , " & " 110 ( BC_2 , DAIP(12) , input , X ) , " & " 111 ( BC_1 , DAIP(13) , output3 , X , 112 , 0 , Z ) , " & " 112 ( BC_1 , * , control , 0 ) , " & " 113 ( BC_2 , DAIP(13) , input , X ) , " & " 114 ( BC_1 , DAIP(14) , output3 , X , 115 , 0 , Z ) , " & " 115 ( BC_1 , * , control , 0 ) , " & " 116 ( BC_2 , DAIP(14) , input , X ) , " & " 117 ( BC_1 , DAIP(15) , output3 , X , 118 , 0 , Z ) , " & " 118 ( BC_1 , * , control , 0 ) , " & " 119 ( BC_2 , DAIP(15) , input , X ) , " & " 120 ( BC_1 , DAIP(16) , output3 , X , 121 , 0 , Z ) , " & " 121 ( BC_1 , * , control , 0 ) , " & " 122 ( BC_2 , DAIP(16) , input , X ) , " & " 123 ( BC_1 , DAIP(17) , output3 , X , 124 , 0 , Z ) , " & " 124 ( BC_1 , * , control , 0 ) , " & " 125 ( BC_2 , DAIP(17) , input , X ) , " & " 126 ( BC_1 , DAIP(18) , output3 , X , 127 , 0 , Z ) , " & " 127 ( BC_1 , * , control , 0 ) , " & " 128 ( BC_2 , DAIP(18) , input , X ) , " & " 129 ( BC_1 , DAIP(19) , output3 , X , 130 , 0 , Z ) , " & " 130 ( BC_1 , * , control , 0 ) , " & " 131 ( BC_2 , DAIP(19) , input , X ) , " & " 132 ( BC_1 , DAIP(20) , output3 , X , 133 , 0 , Z ) , " & " 133 ( BC_1 , * , control , 0 ) , " & " 134 ( BC_2 , DAIP(20) , input , X ) , " & " 135 ( BC_1 , FLAG2 , output3 , X , 136 , 0 , Z ) , " & " 136 ( BC_1 , * , control , 0 ) , " & " 137 ( BC_2 , FLAG2 , input , X ) , " & " 138 ( BC_1 , FLAG3 , output3 , X , 139 , 0 , Z ) , " & " 139 ( BC_1 , * , control , 0 ) , " & " 140 ( BC_2 , FLAG3 , input , X ) , " & " 141 ( BC_3 , * , internal , X ) , " & " 142 ( BC_3 , * , internal , X ) , " & " 143 ( BC_2 , RESET_B , input , X ) , " & " 144 ( BC_3 , * , internal , X ) , " & " 145 ( BC_3 , * , internal , X ) , " & " 146 ( BC_2 , SPIDS_B , input , X ) , " & " 147 ( BC_1 , SPICLK , output3 , X , 148 , 0 , Z ) , " & " 148 ( BC_1 , * , control , 0 ) , " & " 149 ( BC_2 , SPICLK , input , X ) , " & " 150 ( BC_1 , MISO , output3 , X , 151 , 0 , Z ) , " & " 151 ( BC_1 , * , control , 0 ) , " & " 152 ( BC_2 , MISO , input , X ) , " & " 153 ( BC_1 , MOSI , output3 , X , 154 , 0 , Z ) , " & " 154 ( BC_1 , * , control , 0 ) , " & " 155 ( BC_2 , MOSI , input , X ) , " & " 156 ( BC_1 , CLKOUT , output3 , X , 157 , 0 , Z ) , " & " 157 ( BC_1 , * , control , 0 ) , " & " 158 ( BC_2 , CLKOUT , input , X ) , " & " 159 ( BC_1 , EMU_B , output3 , X , 160 , 0 , Z ) , " & " 160 ( BC_1 , * , control , 0 ) , " & " 161 ( BC_2 , EMU_B , input , X ) , " & " 162 ( BC_3 , * , internal , X ) " ; end ADSP_2126x;