-- BSDL for ADSP-2191 -- Digital Signal Processors -- -- Created: 09/11/00 - R. Gutmann -- Updated: 01/22/01 - R. Gutmann changed attribute TAP_SCAN_RESET of TRST_B from false to true -- Updated: 02/28/01 - R. Gutmann changed port CLKIN/XTAL from in to linkage entity ADSP_2191 is generic (PHYSICAL_PIN_MAP : string:="UNDEFINED"); port( RESET: in bit; BYPASS: in bit; BMODE1: in bit; BMODE0: in bit; RFS1: inout bit; RCLK1: inout bit; DR1: in bit; TFS1: inout bit; TCLK1: inout bit; DT1: out bit; RFS0: inout bit; RCLK0: inout bit; DR0: in bit; TFS0: inout bit; TCLK0: inout bit; DT0: out bit; CLKOUT: out bit; TX: out bit; RX: in bit; RFS2: inout bit; RCLK2: inout bit; DR2: inout bit; TFS2: inout bit; TCLK2: inout bit; DT2: inout bit; TMR2: inout bit; TMR1: inout bit; TMR0: inout bit; PF7: inout bit; PF6: inout bit; PF5: inout bit; PF4: inout bit; PF3: inout bit; PF2: inout bit; PF1: inout bit; PF0: inout bit; HCIOMS: in bit; HCMS: in bit; HACK: inout bit; HWR: in bit; HRD: in bit; HALE: in bit; HACKP: in bit; HA16: in bit; HAD: inout bit_vector(0 to 15); DBUS: inout bit_vector(0 to 15); RD: out bit; WR: out bit; ACK: in bit; MS3: out bit; MS2: out bit; MS1: out bit; MS0: out bit; IOMS: out bit; BMS: out bit; BR: in bit; BG: out bit; BGH: out bit; ADDR: out bit_vector(0 to 21); OPMODE: in bit; EMU: out bit; TCK: in bit; TMS: in bit; TDI: in bit; TDO: out bit; TRST_B: in bit; CLKIN: linkage bit; XTAL: linkage bit; IOVDD: linkage bit_vector(0 to 8); VDD: linkage bit_vector(0 to 3); GND: linkage bit_vector(0 to 11)); use STD_1149_1_1990.all; attribute PIN_MAP of ADSP_2191: entity is PHYSICAL_PIN_MAP; constant LQFP_PACKAGE: PIN_MAP_STRING:= "RESET: 73," & "BYPASS: 72," & "BMODE1: 71," & "BMODE0: 70," & "RFS1: 69," & "RCLK1: 68," & "DR1: 67," & "TFS1: 66," & "TCLK1: 65," & "DT1: 64," & "RFS0: 62," & "RCLK0: 61," & "DR0: 60," & "TFS0: 59," & "TCLK0: 57," & "DT0: 56," & "CLKOUT: 130," & "TX: 53," & "RX: 52," & "RFS2: 51," & "RCLK2: 50," & "DR2: 49," & "TFS2: 48," & "TCLK2: 47," & "DT2: 46," & "TMR2: 45," & "TMR1: 44," & "TMR0: 43," & "PF7: 42," & "PF6: 41," & "PF5: 39," & "PF4: 38," & "PF3: 37," & "PF2: 36," & "PF1: 35," & "PF0: 34," & "HCIOMS: 28," & "HCMS: 27," & "HACK: 26," & "HWR: 32," & "HRD: 31," & "HALE: 30," & "HACKP: 24," & "HA16: 23," & "HAD: (3,4,6,7,8,9,10,11,12,14,15,17,18,20,21,22)," & "DBUS: (123,124,125,126,128,135,136,137,138,139,140,141,142,144,1,2)," & "RD: 122," & "WR: 121," & "ACK: 120," & "MS3: 119," & "MS2: 117," & "MS1: 116," & "MS0: 115," & "IOMS: 114," & "BMS: 113," & "BR: 112," & "BG: 111," & "BGH: 110," & "ADDR: (84,85,86,87,88,89,91,92,93,95,96,97,98,99,101,102," & "103,104,106,107,108,109)," & "OPMODE: 83," & "EMU: 81," & "TCK: 78," & "TMS: 76," & "TDI: 75," & "TDO: 74," & "TRST_B: 79," & "CLKIN: 132," & "XTAL: 133," & "IOVDD: (13,25,40,63,90,100,118,131,143)," & "VDD: (19,58,82,127)," & "GND: (5,16,29,33,54,55,77,80,94,105,129,134)" ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST_B : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH); attribute INSTRUCTION_LENGTH of ADSP_2191: entity is 5; -- Unspecified opcodes assigned to Bypass. attribute INSTRUCTION_OPCODE of ADSP_2191: entity is "BYPASS (11111)," & "EXTEST (00000)," & "SAMPLE (10000)," & "IDCODE (00001)," & "INTEST (11000)," & "MEMTEST (01011)," & "EMULATION (01000,10100,00100,01100,00101,00110,00111)"; attribute INSTRUCTION_CAPTURE of ADSP_2191: entity is "00001"; attribute INSTRUCTION_PRIVATE of ADSP_2191: entity is "EMULATION," & "MEMTEST"; attribute IDCODE_REGISTER of ADSP_2191: entity is "0011" & -- Version "0010011110001011" & -- Part number "00011100101" & -- ADI manufacturing code "1"; -- Required bit -- attribute INSTRUCTION_USAGE of ADSP_2191: entity is -- "INTEST (clock CLKIN)"; attribute BOUNDARY_CELLS of ADSP_2191: entity is "BC_1, BC_2, BC_3, BC_4"; -- BC_1: output, control; BC_2: input; BC_3: internal; BC_4: clock; attribute BOUNDARY_LENGTH of ADSP_2191: entity is 299; attribute BOUNDARY_REGISTER of ADSP_2191: entity is --num cell port function safe [ccell disval rslt ] " 0 ( BC_2 , RESET , input , X ) , " & " 1 ( BC_2 , BYPASS , input , X ) , " & " 2 ( BC_2 , BMODE1 , input , X ) , " & " 3 ( BC_2 , BMODE0 , input , X ) , " & " 4 ( BC_1 , * , control , 0 ) , " & " 5 ( BC_1 , RFS1 , output3 , X , 4 , 0 , Z ) , " & " 6 ( BC_2 , RFS1 , input , X ) , " & " 7 ( BC_1 , * , control , 0 ) , " & " 8 ( BC_1 , RCLK1 , output3 , X , 7 , 0 , Z ) , " & " 9 ( BC_2 , RCLK1 , input , X ) , " & " 10 ( BC_2 , DR1 , input , X ) , " & " 11 ( BC_1 , * , control , 0 ) , " & " 12 ( BC_1 , TFS1 , output3 , X , 11 , 0 , Z ) , " & " 13 ( BC_2 , TFS1 , input , X ) , " & " 14 ( BC_1 , * , control , 0 ) , " & " 15 ( BC_1 , TCLK1 , output3 , X , 14 , 0 , Z ) , " & " 16 ( BC_2 , TCLK1 , input , X ) , " & " 17 ( BC_1 , * , control , 0 ) , " & " 18 ( BC_1 , DT1 , output3 , X , 17 , 0 , Z ) , " & " 19 ( BC_1 , * , control , 0 ) , " & " 20 ( BC_1 , RFS0 , output3 , X , 19 , 0 , Z ) , " & " 21 ( BC_2 , RFS0 , input , X ) , " & " 22 ( BC_1 , * , control , 0 ) , " & " 23 ( BC_1 , RCLK0 , output3 , X , 22 , 0 , Z ) , " & " 24 ( BC_2 , RCLK0 , input , X ) , " & " 25 ( BC_2 , DR0 , input , X ) , " & " 26 ( BC_1 , * , control , 0 ) , " & " 27 ( BC_1 , TFS0 , output3 , X , 26 , 0 , Z ) , " & " 28 ( BC_2 , TFS0 , input , X ) , " & " 29 ( BC_1 , * , control , 0 ) , " & " 30 ( BC_1 , TCLK0 , output3 , X , 29 , 0 , Z ) , " & " 31 ( BC_2 , TCLK0 , input , X ) , " & " 32 ( BC_1 , * , control , 0 ) , " & " 33 ( BC_1 , DT0 , output3 , X , 32 , 0 , Z ) , " & " 34 ( BC_1 , * , control , 0 ) , " & " 35 ( BC_1 , CLKOUT , output3 , X , 34 , 0 , Z ) , " & " 36 ( BC_1 , * , control , 0 ) , " & " 37 ( BC_1 , TX , output3 , X , 36 , 0 , Z ) , " & " 38 ( BC_2 , RX , input , X ) , " & " 39 ( BC_3 , * , internal , X ) , " & " 40 ( BC_3 , * , internal , X ) , " & " 41 ( BC_3 , * , internal , X ) , " & " 42 ( BC_1 , * , control , 0 ) , " & " 43 ( BC_1 , RFS2 , output3 , X , 42 , 0 , Z ) , " & " 44 ( BC_2 , RFS2 , input , X ) , " & " 45 ( BC_1 , * , control , 0 ) , " & " 46 ( BC_1 , RCLK2 , output3 , X , 45 , 0 , Z ) , " & " 47 ( BC_2 , RCLK2 , input , X ) , " & " 48 ( BC_1 , * , control , 0 ) , " & " 49 ( BC_1 , DR2 , output3 , X , 48 , 0 , Z ) , " & " 50 ( BC_2 , DR2 , input , X ) , " & " 51 ( BC_1 , * , control , 0 ) , " & " 52 ( BC_1 , TFS2 , output3 , X , 51 , 0 , Z ) , " & " 53 ( BC_2 , TFS2 , input , X ) , " & " 54 ( BC_1 , * , control , 0 ) , " & " 55 ( BC_1 , TCLK2 , output3 , X , 54 , 0 , Z ) , " & " 56 ( BC_2 , TCLK2 , input , X ) , " & " 57 ( BC_1 , * , control , 0 ) , " & " 58 ( BC_1 , DT2 , output3 , X , 57 , 0 , Z ) , " & " 59 ( BC_2 , DT2 , input , X ) , " & " 60 ( BC_3 , * , internal , X ) , " & " 61 ( BC_3 , * , internal , X ) , " & " 62 ( BC_3 , * , internal , X ) , " & " 63 ( BC_1 , * , control , 0 ) , " & " 64 ( BC_1 , TMR2 , output3 , X , 63 , 0 , Z ) , " & " 65 ( BC_2 , TMR2 , input , X ) , " & " 66 ( BC_1 , * , control , 0 ) , " & " 67 ( BC_1 , TMR1 , output3 , X , 66 , 0 , Z ) , " & " 68 ( BC_2 , TMR1 , input , X ) , " & " 69 ( BC_1 , * , control , 0 ) , " & " 70 ( BC_1 , TMR0 , output3 , X , 69 , 0 , Z ) , " & " 71 ( BC_2 , TMR0 , input , X ) , " & " 72 ( BC_1 , * , control , 0 ) , " & " 73 ( BC_1 , PF7 , output3 , X , 72 , 0 , Z ) , " & " 74 ( BC_2 , PF7 , input , X ) , " & " 75 ( BC_1 , * , control , 0 ) , " & " 76 ( BC_1 , PF6 , output3 , X , 75 , 0 , Z ) , " & " 77 ( BC_2 , PF6 , input , X ) , " & " 78 ( BC_1 , * , control , 0 ) , " & " 79 ( BC_1 , PF5 , output3 , X , 78 , 0 , Z ) , " & " 80 ( BC_2 , PF5 , input , X ) , " & " 81 ( BC_3 , * , internal , X ) , " & " 82 ( BC_3 , * , internal , X ) , " & " 83 ( BC_3 , * , internal , X ) , " & " 84 ( BC_3 , * , internal , X ) , " & " 85 ( BC_3 , * , internal , X ) , " & " 86 ( BC_3 , * , internal , X ) , " & " 87 ( BC_1 , * , control , 0 ) , " & " 88 ( BC_1 , PF4 , output3 , X , 87 , 0 , Z ) , " & " 89 ( BC_2 , PF4 , input , X ) , " & " 90 ( BC_1 , * , control , 0 ) , " & " 91 ( BC_1 , PF3 , output3 , X , 90 , 0 , Z ) , " & " 92 ( BC_2 , PF3 , input , X ) , " & " 93 ( BC_3 , * , internal , X ) , " & " 94 ( BC_3 , * , internal , X ) , " & " 95 ( BC_3 , * , internal , X ) , " & " 96 ( BC_1 , * , control , 0 ) , " & " 97 ( BC_1 , PF2 , output3 , X , 96 , 0 , Z ) , " & " 98 ( BC_2 , PF2 , input , X ) , " & " 99 ( BC_1 , * , control , 0 ) , " & " 100 ( BC_1 , PF1 , output3 , X , 99 , 0 , Z ) , " & " 101 ( BC_2 , PF1 , input , X ) , " & " 102 ( BC_1 , * , control , 0 ) , " & " 103 ( BC_1 , PF0 , output3 , X , 102 , 0 , Z ) , " & " 104 ( BC_2 , PF0 , input , X ) , " & " 105 ( BC_3 , * , internal , X ) , " & " 106 ( BC_3 , * , internal , X ) , " & " 107 ( BC_3 , * , internal , X ) , " & " 108 ( BC_2 , HCIOMS , input , X ) , " & " 109 ( BC_2 , HCMS , input , X ) , " & " 110 ( BC_1 , * , control , 0 ) , " & " 111 ( BC_1 , HACK , output3 , X , 110 , 0 , Z ) , " & " 112 ( BC_2 , HACK , input , X ) , " & " 113 ( BC_2 , HWR , input , X ) , " & " 114 ( BC_2 , HRD , input , X ) , " & " 115 ( BC_2 , HALE , input , X ) , " & " 116 ( BC_2 , HACKP , input , X ) , " & " 117 ( BC_2 , HA16 , input , X ) , " & " 118 ( BC_1 , * , control , 0 ) , " & " 119 ( BC_1 , HAD(15) , output3 , X , 118 , 0 , Z ) , " & " 120 ( BC_2 , HAD(15) , input , X ) , " & " 121 ( BC_1 , * , control , 0 ) , " & " 122 ( BC_1 , HAD(14) , output3 , X , 121 , 0 , Z ) , " & " 123 ( BC_2 , HAD(14) , input , X ) , " & " 124 ( BC_1 , * , control , 0 ) , " & " 125 ( BC_1 , HAD(13) , output3 , X , 124 , 0 , Z ) , " & " 126 ( BC_2 , HAD(13) , input , X ) , " & " 127 ( BC_1 , * , control , 0 ) , " & " 128 ( BC_1 , HAD(12) , output3 , X , 127 , 0 , Z ) , " & " 129 ( BC_2 , HAD(12) , input , X ) , " & " 130 ( BC_1 , * , control , 0 ) , " & " 131 ( BC_1 , HAD(11) , output3 , X , 130 , 0 , Z ) , " & " 132 ( BC_2 , HAD(11) , input , X ) , " & " 133 ( BC_1 , * , control , 0 ) , " & " 134 ( BC_1 , HAD(10) , output3 , X , 133 , 0 , Z ) , " & " 135 ( BC_2 , HAD(10) , input , X ) , " & " 136 ( BC_1 , * , control , 0 ) , " & " 137 ( BC_1 , HAD(9) , output3 , X , 136 , 0 , Z ) , " & " 138 ( BC_2 , HAD(9) , input , X ) , " & " 139 ( BC_1 , * , control , 0 ) , " & " 140 ( BC_1 , HAD(8) , output3 , X , 139 , 0 , Z ) , " & " 141 ( BC_2 , HAD(8) , input , X ) , " & " 142 ( BC_1 , * , control , 0 ) , " & " 143 ( BC_1 , HAD(7) , output3 , X , 142 , 0 , Z ) , " & " 144 ( BC_2 , HAD(7) , input , X ) , " & " 145 ( BC_1 , * , control , 0 ) , " & " 146 ( BC_1 , HAD(6) , output3 , X , 145 , 0 , Z ) , " & " 147 ( BC_2 , HAD(6) , input , X ) , " & " 148 ( BC_1 , * , control , 0 ) , " & " 149 ( BC_1 , HAD(5) , output3 , X , 148 , 0 , Z ) , " & " 150 ( BC_2 , HAD(5) , input , X ) , " & " 151 ( BC_1 , * , control , 0 ) , " & " 152 ( BC_1 , HAD(4) , output3 , X , 151 , 0 , Z ) , " & " 153 ( BC_2 , HAD(4) , input , X ) , " & " 154 ( BC_1 , * , control , 0 ) , " & " 155 ( BC_1 , HAD(3) , output3 , X , 154 , 0 , Z ) , " & " 156 ( BC_2 , HAD(3) , input , X ) , " & " 157 ( BC_1 , * , control , 0 ) , " & " 158 ( BC_1 , HAD(2) , output3 , X , 157 , 0 , Z ) , " & " 159 ( BC_2 , HAD(2) , input , X ) , " & " 160 ( BC_1 , * , control , 0 ) , " & " 161 ( BC_1 , HAD(1) , output3 , X , 160 , 0 , Z ) , " & " 162 ( BC_2 , HAD(1) , input , X ) , " & " 163 ( BC_1 , * , control , 0 ) , " & " 164 ( BC_1 , HAD(0) , output3 , X , 163 , 0 , Z ) , " & " 165 ( BC_2 , HAD(0) , input , X ) , " & " 166 ( BC_1 , * , control , 0 ) , " & " 167 ( BC_1 , DBUS(15) , output3 , X , 166 , 0 , Z ) , " & " 168 ( BC_2 , DBUS(15) , input , X ) , " & " 169 ( BC_1 , * , control , 0 ) , " & " 170 ( BC_1 , DBUS(14) , output3 , X , 169 , 0 , Z ) , " & " 171 ( BC_2 , DBUS(14) , input , X ) , " & " 172 ( BC_1 , * , control , 0 ) , " & " 173 ( BC_1 , DBUS(13) , output3 , X , 172 , 0 , Z ) , " & " 174 ( BC_2 , DBUS(13) , input , X ) , " & " 175 ( BC_3 , * , internal , X ) , " & " 176 ( BC_3 , * , internal , X ) , " & " 177 ( BC_3 , * , internal , X ) , " & " 178 ( BC_1 , * , control , 0 ) , " & " 179 ( BC_1 , DBUS(12) , output3 , X , 178 , 0 , Z ) , " & " 180 ( BC_2 , DBUS(12) , input , X ) , " & " 181 ( BC_1 , * , control , 0 ) , " & " 182 ( BC_1 , DBUS(11) , output3 , X , 181 , 0 , Z ) , " & " 183 ( BC_2 , DBUS(11) , input , X ) , " & " 184 ( BC_1 , * , control , 0 ) , " & " 185 ( BC_1 , DBUS(10) , output3 , X , 184 , 0 , Z ) , " & " 186 ( BC_2 , DBUS(10) , input , X ) , " & " 187 ( BC_3 , * , internal , X ) , " & " 188 ( BC_3 , * , internal , X ) , " & " 189 ( BC_3 , * , internal , X ) , " & " 190 ( BC_1 , * , control , 0 ) , " & " 191 ( BC_1 , DBUS(9) , output3 , X , 190 , 0 , Z ) , " & " 192 ( BC_2 , DBUS(9) , input , X ) , " & " 193 ( BC_1 , * , control , 0 ) , " & " 194 ( BC_1 , DBUS(8) , output3 , X , 193 , 0 , Z ) , " & " 195 ( BC_2 , DBUS(8) , input , X ) , " & " 196 ( BC_1 , * , control , 0 ) , " & " 197 ( BC_1 , DBUS(7) , output3 , X , 196 , 0 , Z ) , " & " 198 ( BC_2 , DBUS(7) , input , X ) , " & " 199 ( BC_1 , * , control , 0 ) , " & " 200 ( BC_1 , DBUS(6) , output3 , X , 199 , 0 , Z ) , " & " 201 ( BC_2 , DBUS(6) , input , X ) , " & " 202 ( BC_1 , * , control , 0 ) , " & " 203 ( BC_1 , DBUS(5) , output3 , X , 202 , 0 , Z ) , " & " 204 ( BC_2 , DBUS(5) , input , X ) , " & " 205 ( BC_1 , * , control , 0 ) , " & " 206 ( BC_1 , DBUS(4) , output3 , X , 205 , 0 , Z ) , " & " 207 ( BC_2 , DBUS(4) , input , X ) , " & " 208 ( BC_3 , * , internal , X ) , " & " 209 ( BC_3 , * , internal , X ) , " & " 210 ( BC_1 , * , control , 0 ) , " & " 211 ( BC_1 , DBUS(3) , output3 , X , 210 , 0 , Z ) , " & " 212 ( BC_2 , DBUS(3) , input , X ) , " & " 213 ( BC_1 , * , control , 0 ) , " & " 214 ( BC_1 , DBUS(2) , output3 , X , 213 , 0 , Z ) , " & " 215 ( BC_2 , DBUS(2) , input , X ) , " & " 216 ( BC_1 , * , control , 0 ) , " & " 217 ( BC_1 , DBUS(1) , output3 , X , 216 , 0 , Z ) , " & " 218 ( BC_2 , DBUS(1) , input , X ) , " & " 219 ( BC_1 , * , control , 0 ) , " & " 220 ( BC_1 , DBUS(0) , output3 , X , 219 , 0 , Z ) , " & " 221 ( BC_2 , DBUS(0) , input , X ) , " & " 222 ( BC_1 , * , control , 0 ) , " & " 223 ( BC_1 , RD , output3 , X , 222 , 0 , Z ) , " & " 224 ( BC_1 , * , control , 0 ) , " & " 225 ( BC_1 , WR , output3 , X , 224 , 0 , Z ) , " & " 226 ( BC_2 , ACK , input , X ) , " & " 227 ( BC_1 , * , control , 0 ) , " & " 228 ( BC_1 , MS3 , output3 , X , 227 , 0 , Z ) , " & " 229 ( BC_1 , * , control , 0 ) , " & " 230 ( BC_1 , MS2 , output3 , X , 229 , 0 , Z ) , " & " 231 ( BC_1 , * , control , 0 ) , " & " 232 ( BC_1 , MS1 , output3 , X , 231 , 0 , Z ) , " & " 233 ( BC_1 , * , control , 0 ) , " & " 234 ( BC_1 , MS0 , output3 , X , 233 , 0 , Z ) , " & " 235 ( BC_1 , * , control , 0 ) , " & " 236 ( BC_1 , IOMS , output3 , X , 235 , 0 , Z ) , " & " 237 ( BC_1 , * , control , 0 ) , " & " 238 ( BC_1 , BMS , output3 , X , 237 , 0 , Z ) , " & " 239 ( BC_2 , BR , input , X ) , " & " 240 ( BC_1 , * , control , 0 ) , " & " 241 ( BC_1 , BG , output3 , X , 240 , 0 , Z ) , " & " 242 ( BC_1 , * , control , 0 ) , " & " 243 ( BC_1 , BGH , output3 , X , 242 , 0 , Z ) , " & " 244 ( BC_3 , * , internal , X ) , " & " 245 ( BC_3 , * , internal , X ) , " & " 246 ( BC_1 , * , control , 0 ) , " & " 247 ( BC_1 , ADDR(21) , output3 , X , 246 , 0 , Z ) , " & " 248 ( BC_1 , * , control , 0 ) , " & " 249 ( BC_1 , ADDR(20) , output3 , X , 248 , 0 , Z ) , " & " 250 ( BC_3 , * , internal , X ) , " & " 251 ( BC_3 , * , internal , X ) , " & " 252 ( BC_1 , * , control , 0 ) , " & " 253 ( BC_1 , ADDR(19) , output3 , X , 252 , 0 , Z ) , " & " 254 ( BC_1 , * , control , 0 ) , " & " 255 ( BC_1 , ADDR(18) , output3 , X , 254 , 0 , Z ) , " & " 256 ( BC_1 , * , control , 0 ) , " & " 257 ( BC_1 , ADDR(17) , output3 , X , 256 , 0 , Z ) , " & " 258 ( BC_1 , * , control , 0 ) , " & " 259 ( BC_1 , ADDR(16) , output3 , X , 258 , 0 , Z ) , " & " 260 ( BC_1 , * , control , 0 ) , " & " 261 ( BC_1 , ADDR(15) , output3 , X , 260 , 0 , Z ) , " & " 262 ( BC_1 , * , control , 0 ) , " & " 263 ( BC_1 , ADDR(14) , output3 , X , 262 , 0 , Z ) , " & " 264 ( BC_1 , * , control , 0 ) , " & " 265 ( BC_1 , ADDR(13) , output3 , X , 264 , 0 , Z ) , " & " 266 ( BC_1 , * , control , 0 ) , " & " 267 ( BC_1 , ADDR(12) , output3 , X , 266 , 0 , Z ) , " & " 268 ( BC_3 , * , internal , X ) , " & " 269 ( BC_3 , * , internal , X ) , " & " 270 ( BC_1 , * , control , 0 ) , " & " 271 ( BC_1 , ADDR(11) , output3 , X , 270 , 0 , Z ) , " & " 272 ( BC_1 , * , control , 0 ) , " & " 273 ( BC_1 , ADDR(10) , output3 , X , 272 , 0 , Z ) , " & " 274 ( BC_1 , * , control , 0 ) , " & " 275 ( BC_1 , ADDR(9) , output3 , X , 274 , 0 , Z ) , " & " 276 ( BC_1 , * , control , 0 ) , " & " 277 ( BC_1 , ADDR(8) , output3 , X , 276 , 0 , Z ) , " & " 278 ( BC_1 , * , control , 0 ) , " & " 279 ( BC_1 , ADDR(7) , output3 , X , 278 , 0 , Z ) , " & " 280 ( BC_1 , * , control , 0 ) , " & " 281 ( BC_1 , ADDR(6) , output3 , X , 280 , 0 , Z ) , " & " 282 ( BC_3 , * , internal , X ) , " & " 283 ( BC_3 , * , internal , X ) , " & " 284 ( BC_1 , * , control , 0 ) , " & " 285 ( BC_1 , ADDR(5) , output3 , X , 284 , 0 , Z ) , " & " 286 ( BC_1 , * , control , 0 ) , " & " 287 ( BC_1 , ADDR(4) , output3 , X , 286 , 0 , Z ) , " & " 288 ( BC_1 , * , control , 0 ) , " & " 289 ( BC_1 , ADDR(3) , output3 , X , 288 , 0 , Z ) , " & " 290 ( BC_1 , * , control , 0 ) , " & " 291 ( BC_1 , ADDR(2) , output3 , X , 290 , 0 , Z ) , " & " 292 ( BC_1 , * , control , 0 ) , " & " 293 ( BC_1 , ADDR(1) , output3 , X , 292 , 0 , Z ) , " & " 294 ( BC_1 , * , control , 0 ) , " & " 295 ( BC_1 , ADDR(0) , output3 , X , 294 , 0 , Z ) , " & " 296 ( BC_2 , OPMODE , input , X ) , " & " 297 ( BC_1 , * , control , 0 ) , " & " 298 ( BC_1 , EMU , output3 , X , 297 , 0 , Z ) " ; end ADSP_2191;