---------------------------------------------- -- BSDL for ADSP_BF504(F) LFCSP_PACKAGE -- 88-Lead LFCSP Package -- Revision 0.1 (March 21, 2012) ---------------------------------------------- -- NOTE: -- Due to TWI functionality, drivers for pins SDA and SCL -- are open-drain and therefore can only tri-state or drive 0. Loading -- the output cells with 1 will result in the driver tri-stating. Please keep -- the following in mind: -- - When configuring O/D pins as outputs, internal cells -- 115(SDA) and 118(SCL) must always be -- loaded with 1 -- - When configuring O/D pins as inputs, output2 cells 114(SDA) and -- 117(SCL) must be loaded with 1 -- ---------------------------------------------- entity ADSP_BF50x is generic (PHYSICAL_PIN_MAP : string:="LFCSP_PACKAGE"); port ( SCL: inout bit; SDA: inout bit; PG14: inout bit; PG15: inout bit; PG12: inout bit; PG13: inout bit; PG11: inout bit; PG10: inout bit; PG9: inout bit; PG8: inout bit; PG7: inout bit; PG6: inout bit; PG5: inout bit; PG4: inout bit; PG3: inout bit; PG2: inout bit; PG1: inout bit; PG0: inout bit; PF15: inout bit; PF14: inout bit; PF13: inout bit; PF12: inout bit; PF11: inout bit; PF10: inout bit; RESET: in bit; NMI: in bit; PF9: inout bit; PF8: inout bit; PF7: inout bit; PF6: inout bit; PF5: inout bit; PF4: inout bit; PF3: inout bit; PF2: inout bit; EXTCLK: out bit; PF1: inout bit; PF0: inout bit; PH1: inout bit; PH2: inout bit; PH0: inout bit; BMODE0: in bit; BMODE1: in bit; BMODE2: in bit; EMU: linkage bit; TRST: in bit; TMS: in bit; TCK: in bit; TDI: in bit; PG: linkage bit; EXT_WAKE: linkage bit; VDDFLASH: linkage bit_vector(0 to 2); CLKIN: linkage bit; XTAL: linkage bit; GND: linkage bit_vector(0 to 2); VDDEXT: linkage bit_vector(0 to 15); VDDINT: linkage bit_vector(0 to 5); TDO: out bit); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of ADSP_BF50x: entity is "STD_1149_1_1990"; attribute PIN_MAP of ADSP_BF50x: entity is PHYSICAL_PIN_MAP; constant LFCSP_PACKAGE: PIN_MAP_STRING:= "NMI: 1," & "TRST: 26," & "TMS: 25," & "BMODE0: 51," & "BMODE1: 50," & "TCK: 24," & "BMODE2: 49," & "TDI: 23," & "PH0: 71," & "PH1: 72," & "PH2: 73," & "PF10: 4," & "PF11: 6," & "PF12: 8," & "PF13: 9," & "PF14: 11," & "PF15: 12," & "PG0: 17," & "PG1: 18," & "PG2: 19," & "PG3: 21," & "PG4: 22," & "PG5: 28," & "PG6: 29," & "PG7: 30," & "PG8: 33," & "PG9: 34," & "SCL: 44," & "SDA: 43," & "PG10: 35," & "PG11: 36," & "PG12: 37," & "PG13: 38," & "PG14: 39," & "PF0: 76," & "PG15: 40," & "PF1: 77," & "PF2: 80," & "PF3: 81," & "PF4: 82," & "PF5: 83," & "PF6: 85," & "PF7: 86," & "PF8: 87," & "PF9: 88," & "EXTCLK: 78," & "TDO: 27," & "RESET: 2," & "PG: 63," & "EXT_WAKE: 62," & "EMU: 60," & "CLKIN: 68," & "XTAL: 69," & "VDDEXT: (5,10,13,16,20,31,41,52,54,56,58,59,70,74,79,84)," & "VDDINT: (14,32,42,53,57,75)," & "GND: (3,7,67)," & "VDDFLASH: (15,55,61)"; attribute TAP_SCAN_IN of TDI: signal is true; attribute TAP_SCAN_MODE of TMS: signal is true; attribute TAP_SCAN_OUT of TDO: signal is true; attribute TAP_SCAN_RESET of TRST: signal is true; attribute TAP_SCAN_CLOCK of TCK: signal is (20.0e6, BOTH); attribute INSTRUCTION_LENGTH of ADSP_BF50x: entity is 5; -- Unspecified opcodes assigned to Bypass. attribute INSTRUCTION_OPCODE of ADSP_BF50x: entity is "BYPASS (11111)," & "EXTEST (00000)," & "SAMPLE (10000)," & "IDCODE (00010)," & "PRIVATE (01000, " & " 00100, " & " 10100, " & " 01100, " & " 01010, " & " 00110, " & " 10110, " & " 11110) " ; attribute INSTRUCTION_CAPTURE of ADSP_BF50x: entity is "00001"; attribute INSTRUCTION_PRIVATE of ADSP_BF50x: entity is "PRIVATE"; attribute IDCODE_REGISTER of ADSP_BF50x : entity is --Select your silicon revision "0000" & -- Version: Revision 0.0 --"0001" & -- Version: Revision 0.1 --"0010" & -- Version: Revision 0.2 "0010100000000000" & -- Part Number "00001100101" & -- ADI Manufacturing Code "1"; -- Required Bit attribute BOUNDARY_LENGTH of ADSP_BF50x: entity is 119; attribute BOUNDARY_REGISTER of ADSP_BF50x: entity is --num cell port function safe [ccell disval rslt] " 0 (BC_2, BMODE2, input, X), " & " 1 (BC_2, BMODE1, input, X), " & " 2 (BC_2, BMODE0, input, X), " & " 3 (BC_2, PH0, input, X), " & " 4 (BC_1, PH0, output3, X, 5, 0, Z), " & " 5 (BC_1, *, control, 0), " & " 6 (BC_2, PH2, input, X), " & " 7 (BC_1, PH2, output3, X, 8, 0, Z), " & " 8 (BC_1, *, control, 0), " & " 9 (BC_2, PH1, input, X), " & " 10 (BC_1, PH1, output3, X, 11, 0, Z), " & " 11 (BC_1, *, control, 0), " & " 12 (BC_2, PF0, input, X), " & " 13 (BC_1, PF0, output3, X, 14, 0, Z), " & " 14 (BC_1, *, control, 0), " & " 15 (BC_2, PF1, input, X), " & " 16 (BC_1, PF1, output3, X, 17, 0, Z), " & " 17 (BC_1, *, control, 0), " & " 18 (BC_1, EXTCLK, output3, X, 19, 0, Z), " & " 19 (BC_1, *, control, 0), " & " 20 (BC_2, PF2, input, X), " & " 21 (BC_1, PF2, output3, X, 22, 0, Z), " & " 22 (BC_1, *, control, 0), " & " 23 (BC_2, PF3, input, X), " & " 24 (BC_1, PF3, output3, X, 25, 0, Z), " & " 25 (BC_1, *, control, 0), " & " 26 (BC_2, PF4, input, X), " & " 27 (BC_1, PF4, output3, X, 28, 0, Z), " & " 28 (BC_1, *, control, 0), " & " 29 (BC_2, PF5, input, X), " & " 30 (BC_1, PF5, output3, X, 31, 0, Z), " & " 31 (BC_1, *, control, 0), " & " 32 (BC_2, PF6, input, X), " & " 33 (BC_1, PF6, output3, X, 34, 0, Z), " & " 34 (BC_1, *, control, 0), " & " 35 (BC_2, PF7, input, X), " & " 36 (BC_1, PF7, output3, X, 37, 0, Z), " & " 37 (BC_1, *, control, 0), " & " 38 (BC_2, PF8, input, X), " & " 39 (BC_1, PF8, output3, X, 40, 0, Z), " & " 40 (BC_1, *, control, 0), " & " 41 (BC_2, PF9, input, X), " & " 42 (BC_1, PF9, output3, X, 43, 0, Z), " & " 43 (BC_1, *, control, 0), " & " 44 (BC_2, NMI, input, X), " & " 45 (BC_2, RESET, input, X), " & " 46 (BC_2, *, internal, 0), " & " 47 (BC_2, PF10, input, X), " & " 48 (BC_1, PF10, output3, X, 49, 0, Z), " & " 49 (BC_1, *, control, 0), " & " 50 (BC_2, PF11, input, X), " & " 51 (BC_1, PF11, output3, X, 52, 0, Z), " & " 52 (BC_1, *, control, 0), " & " 53 (BC_2, PF12, input, X), " & " 54 (BC_1, PF12, output3, X, 55, 0, Z), " & " 55 (BC_1, *, control, 0), " & " 56 (BC_2, PF13, input, X), " & " 57 (BC_1, PF13, output3, X, 58, 0, Z), " & " 58 (BC_1, *, control, 0), " & " 59 (BC_2, PF14, input, X), " & " 60 (BC_1, PF14, output3, X, 61, 0, Z), " & " 61 (BC_1, *, control, 0), " & " 62 (BC_2, PF15, input, X), " & " 63 (BC_1, PF15, output3, X, 64, 0, Z), " & " 64 (BC_1, *, control, 0), " & " 65 (BC_2, PG0, input, X), " & " 66 (BC_1, PG0, output3, X, 67, 0, Z), " & " 67 (BC_1, *, control, 0), " & " 68 (BC_2, PG1, input, X), " & " 69 (BC_1, PG1, output3, X, 70, 0, Z), " & " 70 (BC_1, *, control, 0), " & " 71 (BC_2, PG2, input, X), " & " 72 (BC_1, PG2, output3, X, 73, 0, Z), " & " 73 (BC_1, *, control, 0), " & " 74 (BC_2, PG3, input, X), " & " 75 (BC_1, PG3, output3, X, 76, 0, Z), " & " 76 (BC_1, *, control, 0), " & " 77 (BC_2, PG4, input, X), " & " 78 (BC_1, PG4, output3, X, 79, 0, Z), " & " 79 (BC_1, *, control, 0), " & " 80 (BC_2, PG5, input, X), " & " 81 (BC_1, PG5, output3, X, 82, 0, Z), " & " 82 (BC_1, *, control, 0), " & " 83 (BC_2, PG6, input, X), " & " 84 (BC_1, PG6, output3, X, 85, 0, Z), " & " 85 (BC_1, *, control, 0), " & " 86 (BC_2, PG7, input, X), " & " 87 (BC_1, PG7, output3, X, 88, 0, Z), " & " 88 (BC_1, *, control, 0), " & " 89 (BC_2, PG8, input, X), " & " 90 (BC_1, PG8, output3, X, 91, 0, Z), " & " 91 (BC_1, *, control, 0), " & " 92 (BC_2, PG9, input, X), " & " 93 (BC_1, PG9, output3, X, 94, 0, Z), " & " 94 (BC_1, *, control, 0), " & " 95 (BC_2, PG10, input, X), " & " 96 (BC_1, PG10, output3, X, 97, 0, Z), " & " 97 (BC_1, *, control, 0), " & " 98 (BC_2, PG11, input, X), " & " 99 (BC_1, PG11, output3, X, 100, 0, Z), " & " 100 (BC_1, *, control, 0), " & " 101 (BC_2, PG13, input, X), " & " 102 (BC_1, PG13, output3, X, 103, 0, Z), " & " 103 (BC_1, *, control, 0), " & " 104 (BC_2, PG12, input, X), " & " 105 (BC_1, PG12, output3, X, 106, 0, Z), " & " 106 (BC_1, *, control, 0), " & " 107 (BC_2, PG15, input, X), " & " 108 (BC_1, PG15, output3, X, 109, 0, Z), " & " 109 (BC_1, *, control, 0), " & " 110 (BC_2, PG14, input, X), " & " 111 (BC_1, PG14, output3, X, 112, 0, Z), " & " 112 (BC_1, *, control, 0), " & " 113 (BC_2, SDA, input, X), " & " 114 (BC_1, SDA, output2, 1, 114, 1, Weak1), " & " 115 (BC_1, *, internal, 1), " & " 116 (BC_2, SCL, input, X), " & " 117 (BC_1, SCL, output2, 1, 117, 1, Weak1), " & " 118 (BC_1, *, internal, 1)"; end ADSP_BF50x;