---------------------------------------------------------------------- -- BSDL file for: -- -- ADSP_BF549 Digital Signal Processor in mBGA Package -- ---------------------------------------------------------------------- -- Revision: 1.0 -- Date: 08/15/07 -- Revision Summary: -- -- -- NOTE: -- Due to TWI functionality, drivers for bidi pins PORTB[0:1] and PORTE[14:15] -- are open-drain and therefore can only tri-state or drive 0. Loading -- the output cells with 1 will result in the driver tri-stating. Please keep -- the following in mind: -- - When configuring O/D pins as outputs(i.e. for EXTEST), internal cells -- 83(PORTE_14), 86(PORTE_15), 581(PORTB_0), 584(PORTB_1) must always be -- loaded with 1 -- - When configuring O/D pins as inputs, output2 cells 82(PORTE_14), -- 85(PORTE_14), 580(PORTB_0), 583(PORTB_1) must be loaded with 1 -- ---------------------------------------------------------------------- entity ADSP_BF549 is generic (PHYSICAL_PIN_MAP : string := "BGA_PACKAGE"); port ( PORTA_0: inout bit; PORTA_1: inout bit; PORTA_2: inout bit; PORTA_3: inout bit; PORTA_4: inout bit; PORTA_5: inout bit; PORTA_6: inout bit; PORTA_7: inout bit; PORTA_8: inout bit; PORTA_9: inout bit; PORTA_10: inout bit; PORTA_11: inout bit; PORTA_12: inout bit; PORTA_13: inout bit; PORTA_14: inout bit; PORTA_15: inout bit; PORTB_0: inout bit; PORTB_1: inout bit; PORTB_2: inout bit; PORTB_3: inout bit; PORTB_4: inout bit; PORTB_5: inout bit; PORTB_6: inout bit; PORTB_7: inout bit; PORTB_8: inout bit; PORTB_9: inout bit; PORTB_10: inout bit; PORTB_11: inout bit; PORTB_12: inout bit; PORTB_13: inout bit; PORTB_14: inout bit; PORTC_0: inout bit; PORTC_1: inout bit; PORTC_2: inout bit; PORTC_3: inout bit; PORTC_4: inout bit; PORTC_5: inout bit; PORTC_6: inout bit; PORTC_7: inout bit; PORTC_8: inout bit; PORTC_9: inout bit; PORTC_10: inout bit; PORTC_11: inout bit; PORTC_12: inout bit; PORTC_13: inout bit; PORTD_0: inout bit; PORTD_1: inout bit; PORTD_2: inout bit; PORTD_3: inout bit; PORTD_4: inout bit; PORTD_5: inout bit; PORTD_6: inout bit; PORTD_7: inout bit; PORTD_8: inout bit; PORTD_9: inout bit; PORTD_10: inout bit; PORTD_11: inout bit; PORTD_12: inout bit; PORTD_13: inout bit; PORTD_14: inout bit; PORTD_15: inout bit; PORTE_0: inout bit; PORTE_1: inout bit; PORTE_2: inout bit; PORTE_3: inout bit; PORTE_4: inout bit; PORTE_5: inout bit; PORTE_6: inout bit; PORTE_7: inout bit; PORTE_8: inout bit; PORTE_9: inout bit; PORTE_10: inout bit; PORTE_11: inout bit; PORTE_12: inout bit; PORTE_13: inout bit; PORTE_14: inout bit; PORTE_15: inout bit; PORTF_0: inout bit; PORTF_1: inout bit; PORTF_2: inout bit; PORTF_3: inout bit; PORTF_4: inout bit; PORTF_5: inout bit; PORTF_6: inout bit; PORTF_7: inout bit; PORTF_8: inout bit; PORTF_9: inout bit; PORTF_10: inout bit; PORTF_11: inout bit; PORTF_12: inout bit; PORTF_13: inout bit; PORTF_14: inout bit; PORTF_15: inout bit; PORTG_0: inout bit; PORTG_1: inout bit; PORTG_2: inout bit; PORTG_3: inout bit; PORTG_4: inout bit; PORTG_5: inout bit; PORTG_6: inout bit; PORTG_7: inout bit; PORTG_8: inout bit; PORTG_9: inout bit; PORTG_10: inout bit; PORTG_11: inout bit; PORTG_12: inout bit; PORTG_13: inout bit; PORTG_14: inout bit; PORTG_15: inout bit; PORTH_0: inout bit; PORTH_1: inout bit; PORTH_2: inout bit; PORTH_3: inout bit; PORTH_4: inout bit; PORTH_5: inout bit; PORTH_6: inout bit; PORTH_7: inout bit; PORTH_8: inout bit; PORTH_9: inout bit; PORTH_10: inout bit; PORTH_11: inout bit; PORTH_12: inout bit; PORTH_13: inout bit; PORTI_0: inout bit; PORTI_1: inout bit; PORTI_2: inout bit; PORTI_3: inout bit; PORTI_4: inout bit; PORTI_5: inout bit; PORTI_6: inout bit; PORTI_7: inout bit; PORTI_8: inout bit; PORTI_9: inout bit; PORTI_10: inout bit; PORTI_11: inout bit; PORTI_12: inout bit; PORTI_13: inout bit; PORTI_14: inout bit; PORTI_15: inout bit; PORTJ_0: inout bit; PORTJ_1: inout bit; PORTJ_2: inout bit; PORTJ_3: inout bit; PORTJ_4: inout bit; PORTJ_5: inout bit; PORTJ_6: inout bit; PORTJ_7: inout bit; PORTJ_8: inout bit; PORTJ_9: inout bit; PORTJ_10: inout bit; PORTJ_11: inout bit; PORTJ_12: inout bit; PORTJ_13: inout bit; ATAPI_PDIAG: in bit; ABE0B: inout bit; ABE1B: inout bit; CLKOUT: buffer bit; DQ0: inout bit; DQ1: inout bit; DQ2: inout bit; DQ3: inout bit; DQ4: inout bit; DQ5: inout bit; DQ6: inout bit; DQ7: inout bit; DQ8: inout bit; DQ9: inout bit; DQ10: inout bit; DQ11: inout bit; DQ12: inout bit; DQ13: inout bit; DQ14: inout bit; DQ15: inout bit; LDM: buffer bit; UDM: buffer bit; LDQS: inout bit; UDQS: inout bit; BA0: buffer bit; BA1: buffer bit; A0: buffer bit; A1: buffer bit; A2: buffer bit; A3: buffer bit; A4: buffer bit; A5: buffer bit; A6: buffer bit; A7: buffer bit; A8: buffer bit; A9: buffer bit; A10: buffer bit; A11: buffer bit; A12: buffer bit; WE_B: buffer bit; CAS_B: buffer bit; RAS_B: buffer bit; CS0_B: buffer bit; CS1_B: buffer bit; CKE: buffer bit; CK2_B: buffer bit; CK2: buffer bit; CK1_B: buffer bit; CK1: buffer bit; DATA15: inout bit; DATA14: inout bit; DATA13: inout bit; DATA12: inout bit; DATA11: inout bit; DATA10: inout bit; DATA9: inout bit; DATA8: inout bit; DATA7: inout bit; DATA6: inout bit; DATA5: inout bit; DATA4: inout bit; DATA3: inout bit; DATA2: inout bit; DATA1: inout bit; DATA0: inout bit; AWEB: inout bit; AREB: inout bit; RESETB: in bit; NMIB: in bit; AOEB: inout bit; AMS3B: inout bit; AMS2B: inout bit; AMS1B: inout bit; AMS0B: inout bit; ADDR3: inout bit; ADDR2: inout bit; ADDR1: inout bit; MFS: inout bit; BMODE0: in bit; BMODE1: in bit; BMODE2: in bit; BMODE3: in bit; TCK: in bit; TDI: in bit; TDO: out bit; TMS: in bit; TRSTB: in bit; EMU_B: linkage bit; IVDD: linkage bit_vector(0 to 14); EVDD: linkage bit_vector(0 to 31); DVDD: linkage bit_vector(0 to 10); GND: linkage bit_vector(0 to 69); EGND_MC: linkage bit; EGND_MX: linkage bit; EVDD_MC: linkage bit; EVDD_MX: linkage bit; IVDD_MP: linkage bit; IGND_MP: linkage bit; RTCVDD: linkage bit; EXT_WAKE: linkage bit; DDR_VREF: linkage bit; DDR_VSSR: linkage bit; CLKIN: linkage bit; XTAL: linkage bit; RTXI: linkage bit; RTXO: linkage bit; PHYCLK: linkage bit; MLF_M: linkage bit; MLF_P: linkage bit; MXI: linkage bit; MXO: linkage bit; VROUT_A: linkage bit; VROUT_B: linkage bit; USB_DP: linkage bit; USB_DM: linkage bit; USB_ID: linkage bit; USB_RSET: linkage bit; USB_VBUS: linkage bit; USB_VDDA: linkage bit; USB_VDDB: linkage bit; USB_VREF: linkage bit; USB_XI: linkage bit; USB_XO: linkage bit); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of ADSP_BF549 : entity is "STD_1149_1_1990"; attribute PIN_MAP of ADSP_BF549 : entity is PHYSICAL_PIN_MAP; constant BGA_PACKAGE : PIN_MAP_STRING := "GND: (A1, A13, A20, B11, D1, E3, F3, F14, G9, G10, G11, H7, H8, H9, H10, H11, H12, " & "J7, J8, J9, J10, J11, J12, K7, K8, K9, K10, K11, K12, K13, L7, L8, L9, L10, L11, " & "L12, L13, L14, M6, M7, M8, M9, M10, M11, M12, M13, M14, N6, N7, N8, N9, N10, N11, " & "N12, N13, N14, P8, P9, P10, P11, P12, P13, R9, R13, R14, R16, Y1, Y20, U8, V6), " & "EGND_MC: F6, " & "EGND_MX: D4, " & "IGND_MP: E7, " & "IVDD_MP: E8, " & "ADDR2: A2, " & "PORTI_0: A3, " & "PORTI_2: A4, " & "PORTI_4: A5, " & "PORTI_6: A6, " & "PORTI_8: A7, " & "PORTI_11: A8, " & "PORTI_12: A9, " & "AMS0B: A10, " & "CLKIN: A11, " & "XTAL: A12, " & "RTXI: A14, " & "DATA4: A15, " & "DATA6: A16, " & "DATA10: A17, " & "VROUT_A: A18, " & "VROUT_B: A19, " & "USB_VREF: B1, " & "ADDR1: B2, " & "ADDR3: B3, " & "PORTI_1: B4, " & "PORTI_3: B5, " & "PORTI_5: B6, " & "PORTI_7: B7, " & "PORTI_10: B8, " & "PORTI_15: B9, " & "AMS2B: B10, " & "AREB: B12, " & "DATA2: B13, " & "RTXO: B14, " & "DATA3: B15, " & "DATA5: B16, " & "DATA7: B17, " & "CKE: B18, " & "CS1_B: B19, " & "A10: B20, " & "MXO: C1, " & "MXI: C2, " & "PORTH_5: C3, " & "PORTH_9: C4, " & "PORTH_11: C5, " & "PORTH_13: C6, " & "PORTH_10: C7, " & "PORTI_9: C8, " & "PORTI_13: C9, " & "AOEB: C10, " & "NMIB: C11, " & "RESETB: C12, " & "DATA1: C13, " & "DATA8: C14, " & "DATA9: C15, " & "ABE1B: C16, " & "ABE0B: C17, " & "CK2: C18, " & "CS0_B: C19, " & "A7: C20, " & "USB_VBUS: D2, " & "USB_RSET: D3, " & "PORTH_8: D5, " & "PORTH_6: D6, " & "PORTH_12: D7, " & "PORTI_14: D8, " & "AMS1B: D9, " & "AMS3B: D10, " & "PHYCLK: D11, " & "AWEB: D12, " & "DATA0: D13, " & "DATA11: D14, " & "DATA12: D15, " & "CK1: D16, " & "DATA15: D17, " & "CK2_B: D18, " & "A12: D19, " & "A6: D20, " & "USB_DP: E1, " & "USB_DM: E2, " & "MLF_P: E4, " & "EVDD: (E9, E10, E11, E12, F8, F13, G5, G6, G7, G14, H5, H6, K6, M15, N5, N15, P15, R6, " & "R7, R8, R15, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, F15), " & "EVDD_MC: F7, " & "EVDD_MX: E5, " & "MFS: E6, " & "IVDD: (F9, G8, G12, G13, J6, J13, L6, L15, P6, P7, P14, R10, R11, R12, U9), " & "RTCVDD: E13, " & "DATA14: E14, " & "DATA13: E15, " & "CK1_B: E16, " & "RAS_B: E17, " & "WE_B: E18, " & "A9: E19, " & "A2: E20, " & "USB_XI: F1, " & "USB_XO: F2, " & "MLF_M: F4, " & "USB_VDDB: F5, " & "DVDD: (F10, F11, F12, G15, H13, H14, H15, J14, J15, K14, K15), " & "CAS_B: F16, " & "A11: F17, " & "A8: F18, " & "A5: F19, " & "LDQS: F20, " & "PORTC_5: G1, " & "PORTC_4: G2, " & "USB_ID: G3, " & "USB_VDDA: G4, " & "A4: G16, " & "A1: G17, " & "A3: G18, " & "A0: G19, " & "LDM: G20, " & "PORTC_3: H1, " & "PORTC_0: H2, " & "PORTC_7: H3, " & "PORTH_7: H4, " & "BA1: H16, " & "BA0: H17, " & "UDQS: H18, " & "UDM: H19, " & "DQ11: H20, " & "PORTF_1: J1, " & "PORTC_2: J2, " & "PORTC_1: J3, " & "PORTG_0: J4, " & "PORTC_6: J5, " & "DQ15: J16, " & "DQ14: J17, " & "DQ13: J18, " & "DQ12: J19, " & "DQ9: J20, " & "PORTF_3: K1, " & "PORTF_2: K2, " & "PORTF_0: K3, " & "PORTF_7: K4, " & "PORTG_1: K5, " & "DQ5: K16, " & "DQ7: K17, " & "DQ10: K18, " & "DQ8: K19, " & "DQ6: K20, " & "PORTF_5: L1, " & "PORTF_4: L2, " & "PORTF_8: L3, " & "PORTF_6: L4, " & "PORTG_2: L5, " & "CLKOUT: L16, " & "DQ4: L17, " & "DQ0: L18, " & "DQ2: L19, " & "DQ3: L20, " & "PORTF_9: M1, " & "PORTF_10: M2, " & "PORTF_11: M3, " & "PORTF_12: M4, " & "PORTE_12: M5, " & "PORTJ_2: M16, " & "PORTJ_11: M17, " & "EXT_WAKE: M18, " & "DQ1: M19, " & "DDR_VREF: M20, " & "PORTF_14: N1, " & "PORTF_15: N2, " & "PORTG_3: N3, " & "PORTF_13: N4, " & "PORTJ_7: N16, " & "PORTJ_4: N17, " & "PORTJ_1: N18, " & "PORTJ_13: N19, " & "DDR_VSSR: N20, " & "PORTG_4: P1, " & "PORTE_11: P2, " & "PORTD_0: P3, " & "PORTD_1: P4, " & "PORTE_13: P5, " & "PORTG_12: P16, " & "PORTJ_9: P17, " & "PORTJ_6: P18, " & "ATAPI_PDIAG: P19, " & "PORTJ_12: P20, " & "PORTD_2: R1, " & "PORTD_3: R2, " & "PORTD_5: R3, " & "PORTD_7: R4, " & "EMU_B: R5, " & "PORTE_7: R17, " & "PORTG_13: R18, " & "PORTJ_8: R19, " & "PORTJ_0: R20, " & "PORTD_4: T1, " & "PORTD_6: T2, " & "PORTD_10: T3, " & "PORTD_12: T4, " & "TRSTB: T5, " & "PORTB_2: T6, " & "PORTE_1: T17, " & "PORTE_10: T18, " & "PORTJ_10: T19, " & "PORTJ_3: T20, " & "PORTD_8: U1, " & "PORTD_9: U2, " & "PORTD_15: U3, " & "PORTD_14: U4, " & "TMS: U5, " & "PORTB_3: U6, " & "PORTB_10: U7, " & "PORTA_8: U10, " & "PORTA_7: U11, " & "PORTA_0: U12, " & "PORTC_10: U13, " & "PORTH_1: U14, " & "PORTG_11: U15, " & "PORTE_14: U16, " & "PORTH_4: U17, " & "PORTE_2: U18, " & "PORTE_9: U19, " & "PORTJ_5: U20, " & "PORTD_11: V1, " & "PORTD_13: V2, " & "TCK: V3, " & "TDO: V4, " & "TDI: V5, " & "PORTB_7: V7, " & "PORTB_9: V8, " & "PORTB_13: V9, " & "PORTA_11: V10, " & "PORTA_5: V11, " & "PORTA_1: V12, " & "PORTC_9: V13, " & "PORTE_3: V14, " & "PORTG_5: V15, " & "PORTG_8: V16, " & "PORTH_2: V17, " & "PORTH_3: V18, " & "PORTE_0: V19, " & "PORTE_8: V20, " & "BMODE0: W1, " & "BMODE1: W2, " & "BMODE2: W3, " & "BMODE3: W4, " & "PORTB_0: W5, " & "PORTB_6: W6, " & "PORTB_11: W7, " & "PORTB_8: W8, " & "PORTA_15: W9, " & "PORTA_13: W10, " & "PORTA_4: W11, " & "PORTA_2: W12, " & "PORTG_15: W13, " & "PORTC_11: W14, " & "PORTC_13: W15, " & "PORTG_7: W16, " & "PORTE_15: W17, " & "PORTH_0: W18, " & "PORTE_6: W19, " & "PORTE_5: W20, " & "PORTB_1: Y2, " & "PORTB_5: Y3, " & "PORTB_4: Y4, " & "PORTB_14: Y5, " & "PORTB_12: Y6, " & "PORTA_14: Y7, " & "PORTA_12: Y8, " & "PORTA_10: Y9, " & "PORTA_9: Y10, " & "PORTA_6: Y11, " & "PORTA_3: Y12, " & "PORTG_14: Y13, " & "PORTC_8: Y14, " & "PORTC_12: Y15, " & "PORTE_4: Y16, " & "PORTG_6: Y17, " & "PORTG_10: Y18, " & "PORTG_9: Y19 "; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_RESET of TRSTB : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH); attribute INSTRUCTION_LENGTH of ADSP_BF549 : entity is 5; attribute INSTRUCTION_OPCODE of ADSP_BF549 : entity is "EXTEST (00000)," & "SAMPLE (10000)," & "IDCODE (00010)," & "EMULATION (00100, 01000, 01100, 10100, 11110)," & "BYPASS (11111)"; attribute INSTRUCTION_CAPTURE of ADSP_BF549 : entity is "00001"; attribute INSTRUCTION_PRIVATE of ADSP_BF549 : entity is "EMULATION"; attribute IDCODE_REGISTER of ADSP_BF549 : entity is "00000010011111011110000011001011"; attribute BOUNDARY_LENGTH of ADSP_BF549 : entity is 636; attribute BOUNDARY_REGISTER of ADSP_BF549 : entity is -- num cell port func safe [ccell dis rslt] "0 (BC_2, PORTA_9, input, X)," & "1 (BC_1, PORTA_9, output3, X, 2, 0, Z)," & "2 (BC_1, *, control, 0)," & "3 (BC_2, PORTA_8, input, X)," & "4 (BC_1, PORTA_8, output3, X, 5, 0, Z)," & "5 (BC_1, *, control, 0)," & "6 (BC_2, PORTA_7, input, X)," & "7 (BC_1, PORTA_7, output3, X, 8, 0, Z)," & "8 (BC_1, *, control, 0)," & "9 (BC_2, PORTA_6, input, X)," & "10 (BC_1, PORTA_6, output3, X, 11, 0, Z)," & "11 (BC_1, *, control, 0)," & "12 (BC_2, PORTA_5, input, X)," & "13 (BC_1, PORTA_5, output3, X, 14, 0, Z)," & "14 (BC_1, *, control, 0)," & "15 (BC_2, PORTA_4, input, X)," & "16 (BC_1, PORTA_4, output3, X, 17, 0, Z)," & "17 (BC_1, *, control, 0)," & "18 (BC_2, PORTA_3, input, X)," & "19 (BC_1, PORTA_3, output3, X, 20, 0, Z)," & -- num cell port func safe [ccell dis rslt] "20 (BC_1, *, control, 0)," & "21 (BC_2, PORTA_2, input, X)," & "22 (BC_1, PORTA_2, output3, X, 23, 0, Z)," & "23 (BC_1, *, control, 0)," & "24 (BC_2, PORTA_1, input, X)," & "25 (BC_1, PORTA_1, output3, X, 26, 0, Z)," & "26 (BC_1, *, control, 0)," & "27 (BC_2, PORTA_0, input, X)," & "28 (BC_1, PORTA_0, output3, X, 29, 0, Z)," & "29 (BC_1, *, control, 0)," & "30 (BC_2, PORTG_14, input, X)," & "31 (BC_1, PORTG_14, output3, X, 32, 0, Z)," & "32 (BC_1, *, control, 0)," & "33 (BC_2, PORTG_15, input, X)," & "34 (BC_1, PORTG_15, output3, X, 35, 0, Z)," & "35 (BC_1, *, control, 0)," & "36 (BC_2, PORTC_8, input, X)," & "37 (BC_1, PORTC_8, output3, X, 38, 0, Z)," & "38 (BC_1, *, control, 0)," & "39 (BC_2, PORTC_9, input, X)," & -- num cell port func safe [ccell dis rslt] "40 (BC_1, PORTC_9, output3, X, 41, 0, Z)," & "41 (BC_1, *, control, 0)," & "42 (BC_2, PORTC_10, input, X)," & "43 (BC_1, PORTC_10, output3, X, 44, 0, Z)," & "44 (BC_1, *, control, 0)," & "45 (BC_2, PORTC_11, input, X)," & "46 (BC_1, PORTC_11, output3, X, 47, 0, Z)," & "47 (BC_1, *, control, 0)," & "48 (BC_2, PORTC_12, input, X)," & "49 (BC_1, PORTC_12, output3, X, 50, 0, Z)," & "50 (BC_1, *, control, 0)," & "51 (BC_2, PORTC_13, input, X)," & "52 (BC_1, PORTC_13, output3, X, 53, 0, Z)," & "53 (BC_1, *, control, 0)," & "54 (BC_2, PORTH_1, input, X)," & "55 (BC_1, PORTH_1, output3, X, 56, 0, Z)," & "56 (BC_1, *, control, 0)," & "57 (BC_2, PORTE_3, input, X)," & "58 (BC_1, PORTE_3, output3, X, 59, 0, Z)," & "59 (BC_1, *, control, 0)," & -- num cell port func safe [ccell dis rslt] "60 (BC_2, PORTG_7, input, X)," & "61 (BC_1, PORTG_7, output3, X, 62, 0, Z)," & "62 (BC_1, *, control, 0)," & "63 (BC_2, PORTG_6, input, X)," & "64 (BC_1, PORTG_6, output3, X, 65, 0, Z)," & "65 (BC_1, *, control, 0)," & "66 (BC_2, PORTG_5, input, X)," & "67 (BC_1, PORTG_5, output3, X, 68, 0, Z)," & "68 (BC_1, *, control, 0)," & "69 (BC_2, PORTG_11, input, X)," & "70 (BC_1, PORTG_11, output3, X, 71, 0, Z)," & "71 (BC_1, *, control, 0)," & "72 (BC_2, PORTG_10, input, X)," & "73 (BC_1, PORTG_10, output3, X, 74, 0, Z)," & "74 (BC_1, *, control, 0)," & "75 (BC_2, PORTG_9, input, X)," & "76 (BC_1, PORTG_9, output3, X, 77, 0, Z)," & "77 (BC_1, *, control, 0)," & "78 (BC_2, PORTG_8, input, X)," & "79 (BC_1, PORTG_8, output3, X, 80, 0, Z)," & -- num cell port func safe [ccell dis rslt] "80 (BC_1, *, control, 0)," & "81 (BC_2, PORTE_14, input, X)," & "82 (BC_1, PORTE_14, output2, 1, 82, 1, WEAK1)," & "83 (BC_1, *, internal, 1)," & "84 (BC_2, PORTE_15, input, X)," & "85 (BC_1, PORTE_15, output2, 1, 85, 1, WEAK1)," & "86 (BC_1, *, internal, 1)," & "87 (BC_2, PORTH_0, input, X)," & "88 (BC_1, PORTH_0, output3, X, 89, 0, Z)," & "89 (BC_1, *, control, 0)," & "90 (BC_2, PORTH_2, input, X)," & "91 (BC_1, PORTH_2, output3, X, 92, 0, Z)," & "92 (BC_1, *, control, 0)," & "93 (BC_2, PORTH_3, input, X)," & "94 (BC_1, PORTH_3, output3, X, 95, 0, Z)," & "95 (BC_1, *, control, 0)," & "96 (BC_2, PORTH_4, input, X)," & "97 (BC_1, PORTH_4, output3, X, 98, 0, Z)," & "98 (BC_1, *, control, 0)," & "99 (BC_2, PORTE_6, input, X)," & -- num cell port func safe [ccell dis rslt] "100 (BC_1, PORTE_6, output3, X, 101, 0, Z)," & "101 (BC_1, *, control, 0)," & "102 (BC_2, PORTE_5, input, X)," & "103 (BC_1, PORTE_5, output3, X, 104, 0, Z)," & "104 (BC_1, *, control, 0)," & "105 (BC_2, PORTE_4, input, X)," & "106 (BC_1, PORTE_4, output3, X, 107, 0, Z)," & "107 (BC_1, *, control, 0)," & "108 (BC_2, PORTE_2, input, X)," & "109 (BC_1, PORTE_2, output3, X, 110, 0, Z)," & "110 (BC_1, *, control, 0)," & "111 (BC_2, PORTE_1, input, X)," & "112 (BC_1, PORTE_1, output3, X, 113, 0, Z)," & "113 (BC_1, *, control, 0)," & "114 (BC_2, PORTE_0, input, X)," & "115 (BC_1, PORTE_0, output3, X, 116, 0, Z)," & "116 (BC_1, *, control, 0)," & "117 (BC_2, PORTE_10, input, X)," & "118 (BC_1, PORTE_10, output3, X, 119, 0, Z)," & "119 (BC_1, *, control, 0)," & -- num cell port func safe [ccell dis rslt] "120 (BC_2, PORTE_9, input, X)," & "121 (BC_1, PORTE_9, output3, X, 122, 0, Z)," & "122 (BC_1, *, control, 0)," & "123 (BC_2, PORTE_8, input, X)," & "124 (BC_1, PORTE_8, output3, X, 125, 0, Z)," & "125 (BC_1, *, control, 0)," & "126 (BC_2, PORTE_7, input, X)," & "127 (BC_1, PORTE_7, output3, X, 128, 0, Z)," & "128 (BC_1, *, control, 0)," & "129 (BC_2, PORTG_12, input, X)," & "130 (BC_1, PORTG_12, output3, X, 131, 0, Z)," & "131 (BC_1, *, control, 0)," & "132 (BC_2, PORTG_13, input, X)," & "133 (BC_1, PORTG_13, output3, X, 134, 0, Z)," & "134 (BC_1, *, control, 0)," & "135 (BC_2, PORTJ_10, input, X)," & "136 (BC_1, PORTJ_10, output3, X, 137, 0, Z)," & "137 (BC_1, *, control, 0)," & "138 (BC_2, PORTJ_9, input, X)," & "139 (BC_1, PORTJ_9, output3, X, 140, 0, Z)," & -- num cell port func safe [ccell dis rslt] "140 (BC_1, *, control, 0)," & "141 (BC_2, PORTJ_8, input, X)," & "142 (BC_1, PORTJ_8, output3, X, 143, 0, Z)," & "143 (BC_1, *, control, 0)," & "144 (BC_2, PORTJ_7, input, X)," & "145 (BC_1, PORTJ_7, output3, X, 146, 0, Z)," & "146 (BC_1, *, control, 0)," & "147 (BC_2, PORTJ_6, input, X)," & "148 (BC_1, PORTJ_6, output3, X, 149, 0, Z)," & "149 (BC_1, *, control, 0)," & "150 (BC_2, PORTJ_5, input, X)," & "151 (BC_1, PORTJ_5, output3, X, 152, 0, Z)," & "152 (BC_1, *, control, 0)," & "153 (BC_2, ATAPI_PDIAG, input, X)," & "154 (BC_2, PORTJ_4, input, X)," & "155 (BC_1, PORTJ_4, output3, X, 156, 0, Z)," & "156 (BC_1, *, control, 0)," & "157 (BC_2, PORTJ_3, input, X)," & "158 (BC_1, PORTJ_3, output3, X, 159, 0, Z)," & "159 (BC_1, *, control, 0)," & -- num cell port func safe [ccell dis rslt] "160 (BC_2, PORTJ_2, input, X)," & "161 (BC_1, PORTJ_2, output3, X, 162, 0, Z)," & "162 (BC_1, *, control, 0)," & "163 (BC_2, PORTJ_1, input, X)," & "164 (BC_1, PORTJ_1, output3, X, 165, 0, Z)," & "165 (BC_1, *, control, 0)," & "166 (BC_2, PORTJ_0, input, X)," & "167 (BC_1, PORTJ_0, output3, X, 168, 0, Z)," & "168 (BC_1, *, control, 0)," & "169 (BC_2, PORTJ_13, input, X)," & "170 (BC_1, PORTJ_13, output3, X, 171, 0, Z)," & "171 (BC_1, *, control, 0)," & "172 (BC_2, PORTJ_12, input, X)," & "173 (BC_1, PORTJ_12, output3, X, 174, 0, Z)," & "174 (BC_1, *, control, 0)," & "175 (BC_2, PORTJ_11, input, X)," & "176 (BC_1, PORTJ_11, output3, X, 177, 0, Z)," & "177 (BC_1, *, control, 0)," & "178 (BC_1, CLKOUT, output2, X)," & "179 (BC_2, DQ0, input, X)," & -- num cell port func safe [ccell dis rslt] "180 (BC_1, DQ0, output3, X, 181, 0, Z)," & "181 (BC_1, *, control, 0)," & "182 (BC_2, DQ1, input, X)," & "183 (BC_1, DQ1, output3, X, 184, 0, Z)," & "184 (BC_1, *, control, 0)," & "185 (BC_2, DQ2, input, X)," & "186 (BC_1, DQ2, output3, X, 187, 0, Z)," & "187 (BC_1, *, control, 0)," & "188 (BC_2, DQ3, input, X)," & "189 (BC_1, DQ3, output3, X, 190, 0, Z)," & "190 (BC_1, *, control, 0)," & "191 (BC_2, DQ4, input, X)," & "192 (BC_1, DQ4, output3, X, 193, 0, Z)," & "193 (BC_1, *, control, 0)," & "194 (BC_2, DQ5, input, X)," & "195 (BC_1, DQ5, output3, X, 196, 0, Z)," & "196 (BC_1, *, control, 0)," & "197 (BC_2, DQ6, input, X)," & "198 (BC_1, DQ6, output3, X, 199, 0, Z)," & "199 (BC_1, *, control, 0)," & -- num cell port func safe [ccell dis rslt] "200 (BC_2, DQ7, input, X)," & "201 (BC_1, DQ7, output3, X, 202, 0, Z)," & "202 (BC_1, *, control, 0)," & "203 (BC_2, DQ8, input, X)," & "204 (BC_1, DQ8, output3, X, 205, 0, Z)," & "205 (BC_1, *, control, 0)," & "206 (BC_2, DQ9, input, X)," & "207 (BC_1, DQ9, output3, X, 208, 0, Z)," & "208 (BC_1, *, control, 0)," & "209 (BC_2, DQ10, input, X)," & "210 (BC_1, DQ10, output3, X, 211, 0, Z)," & "211 (BC_1, *, control, 0)," & "212 (BC_2, DQ11, input, X)," & "213 (BC_1, DQ11, output3, X, 214, 0, Z)," & "214 (BC_1, *, control, 0)," & "215 (BC_2, DQ12, input, X)," & "216 (BC_1, DQ12, output3, X, 217, 0, Z)," & "217 (BC_1, *, control, 0)," & "218 (BC_2, DQ13, input, X)," & "219 (BC_1, DQ13, output3, X, 220, 0, Z)," & -- num cell port func safe [ccell dis rslt] "220 (BC_1, *, control, 0)," & "221 (BC_2, DQ14, input, X)," & "222 (BC_1, DQ14, output3, X, 223, 0, Z)," & "223 (BC_1, *, control, 0)," & "224 (BC_2, DQ15, input, X)," & "225 (BC_1, DQ15, output3, X, 226, 0, Z)," & "226 (BC_1, *, control, 0)," & "227 (BC_1, LDM, output2, X)," & "228 (BC_1, UDM, output2, X)," & "229 (BC_2, LDQS, input, X)," & "230 (BC_1, LDQS, output3, X, 231, 0, Z)," & "231 (BC_1, *, control, 0)," & "232 (BC_2, UDQS, input, X)," & "233 (BC_1, UDQS, output3, X, 234, 0, Z)," & "234 (BC_1, *, control, 0)," & "235 (BC_1, BA0, output2, X)," & "236 (BC_1, BA1, output2, X)," & "237 (BC_1, A0, output2, X)," & "238 (BC_1, A1, output2, X)," & "239 (BC_1, A2, output2, X)," & -- num cell port func safe [ccell dis rslt] "240 (BC_1, A3, output2, X)," & "241 (BC_1, A4, output2, X)," & "242 (BC_1, A5, output2, X)," & "243 (BC_1, A6, output2, X)," & "244 (BC_1, A7, output2, X)," & "245 (BC_1, A8, output2, X)," & "246 (BC_1, A9, output2, X)," & "247 (BC_1, A10, output2, X)," & "248 (BC_1, A11, output2, X)," & "249 (BC_1, A12, output2, X)," & "250 (BC_1, WE_B, output2, X)," & "251 (BC_1, CAS_B, output2, X)," & "252 (BC_1, RAS_B, output2, X)," & "253 (BC_1, CS0_B, output2, X)," & "254 (BC_1, CS1_B, output2, X)," & "255 (BC_1, CKE, output2, X)," & "256 (BC_1, CK2_B, output2, X)," & "257 (BC_1, CK2, output2, X)," & "258 (BC_1, CK1_B, output2, X)," & "259 (BC_1, CK1, output2, X)," & -- num cell port func safe [ccell dis rslt] "260 (BC_2, ABE0B, input, X)," & "261 (BC_1, ABE0B, output3, X, 262, 0, Z)," & "262 (BC_1, *, control, 0)," & "263 (BC_2, ABE1B, input, X)," & "264 (BC_1, ABE1B, output3, X, 265, 0, Z)," & "265 (BC_1, *, control, 0)," & "266 (BC_2, DATA15, input, X)," & "267 (BC_1, DATA15, output3, X, 268, 0, Z)," & "268 (BC_1, *, control, 0)," & "269 (BC_2, DATA14, input, X)," & "270 (BC_1, DATA14, output3, X, 271, 0, Z)," & "271 (BC_1, *, control, 0)," & "272 (BC_2, DATA13, input, X)," & "273 (BC_1, DATA13, output3, X, 274, 0, Z)," & "274 (BC_1, *, control, 0)," & "275 (BC_2, DATA12, input, X)," & "276 (BC_1, DATA12, output3, X, 277, 0, Z)," & "277 (BC_1, *, control, 0)," & "278 (BC_2, DATA11, input, X)," & "279 (BC_1, DATA11, output3, X, 280, 0, Z)," & -- num cell port func safe [ccell dis rslt] "280 (BC_1, *, control, 0)," & "281 (BC_2, DATA10, input, X)," & "282 (BC_1, DATA10, output3, X, 283, 0, Z)," & "283 (BC_1, *, control, 0)," & "284 (BC_2, DATA9, input, X)," & "285 (BC_1, DATA9, output3, X, 286, 0, Z)," & "286 (BC_1, *, control, 0)," & "287 (BC_2, DATA8, input, X)," & "288 (BC_1, DATA8, output3, X, 289, 0, Z)," & "289 (BC_1, *, control, 0)," & "290 (BC_2, DATA7, input, X)," & "291 (BC_1, DATA7, output3, X, 292, 0, Z)," & "292 (BC_1, *, control, 0)," & "293 (BC_2, DATA6, input, X)," & "294 (BC_1, DATA6, output3, X, 295, 0, Z)," & "295 (BC_1, *, control, 0)," & "296 (BC_2, DATA5, input, X)," & "297 (BC_1, DATA5, output3, X, 298, 0, Z)," & "298 (BC_1, *, control, 0)," & "299 (BC_2, DATA4, input, X)," & -- num cell port func safe [ccell dis rslt] "300 (BC_1, DATA4, output3, X, 301, 0, Z)," & "301 (BC_1, *, control, 0)," & "302 (BC_2, DATA3, input, X)," & "303 (BC_1, DATA3, output3, X, 304, 0, Z)," & "304 (BC_1, *, control, 0)," & "305 (BC_2, DATA2, input, X)," & "306 (BC_1, DATA2, output3, X, 307, 0, Z)," & "307 (BC_1, *, control, 0)," & "308 (BC_2, DATA1, input, X)," & "309 (BC_1, DATA1, output3, X, 310, 0, Z)," & "310 (BC_1, *, control, 0)," & "311 (BC_2, DATA0, input, X)," & "312 (BC_1, DATA0, output3, X, 313, 0, Z)," & "313 (BC_1, *, control, 0)," & "314 (BC_2, AWEB, input, X)," & "315 (BC_1, AWEB, output3, X, 316, 0, Z)," & "316 (BC_1, *, control, 0)," & "317 (BC_2, AREB, input, X)," & "318 (BC_1, AREB, output3, X, 319, 0, Z)," & "319 (BC_1, *, control, 0)," & -- num cell port func safe [ccell dis rslt] "320 (BC_2, RESETB, input, 1)," & "321 (BC_2, NMIB, input, X)," & "322 (BC_2, AOEB, input, X)," & "323 (BC_1, AOEB, output3, X, 324, 0, Z)," & "324 (BC_1, *, control, 0)," & "325 (BC_2, AMS3B, input, X)," & "326 (BC_1, AMS3B, output3, X, 327, 0, Z)," & "327 (BC_1, *, control, 0)," & "328 (BC_2, AMS2B, input, X)," & "329 (BC_1, AMS2B, output3, X, 330, 0, Z)," & "330 (BC_1, *, control, 0)," & "331 (BC_2, AMS1B, input, X)," & "332 (BC_1, AMS1B, output3, X, 333, 0, Z)," & "333 (BC_1, *, control, 0)," & "334 (BC_2, AMS0B, input, X)," & "335 (BC_1, AMS0B, output3, X, 336, 0, Z)," & "336 (BC_1, *, control, 0)," & "337 (BC_2, PORTI_15, input, X)," & "338 (BC_1, PORTI_15, output3, X, 339, 0, Z)," & "339 (BC_1, *, control, 0)," & -- num cell port func safe [ccell dis rslt] "340 (BC_2, PORTI_14, input, X)," & "341 (BC_1, PORTI_14, output3, X, 342, 0, Z)," & "342 (BC_1, *, control, 0)," & "343 (BC_2, PORTI_13, input, X)," & "344 (BC_1, PORTI_13, output3, X, 345, 0, Z)," & "345 (BC_1, *, control, 0)," & "346 (BC_2, PORTI_12, input, X)," & "347 (BC_1, PORTI_12, output3, X, 348, 0, Z)," & "348 (BC_1, *, control, 0)," & "349 (BC_2, PORTI_11, input, X)," & "350 (BC_1, PORTI_11, output3, X, 351, 0, Z)," & "351 (BC_1, *, control, 0)," & "352 (BC_2, PORTI_10, input, X)," & "353 (BC_1, PORTI_10, output3, X, 354, 0, Z)," & "354 (BC_1, *, control, 0)," & "355 (BC_2, PORTI_9, input, X)," & "356 (BC_1, PORTI_9, output3, X, 357, 0, Z)," & "357 (BC_1, *, control, 0)," & "358 (BC_2, PORTI_8, input, X)," & "359 (BC_1, PORTI_8, output3, X, 360, 0, Z)," & -- num cell port func safe [ccell dis rslt] "360 (BC_1, *, control, 0)," & "361 (BC_2, PORTI_7, input, X)," & "362 (BC_1, PORTI_7, output3, X, 363, 0, Z)," & "363 (BC_1, *, control, 0)," & "364 (BC_2, PORTI_6, input, X)," & "365 (BC_1, PORTI_6, output3, X, 366, 0, Z)," & "366 (BC_1, *, control, 0)," & "367 (BC_2, PORTI_5, input, X)," & "368 (BC_1, PORTI_5, output3, X, 369, 0, Z)," & "369 (BC_1, *, control, 0)," & "370 (BC_2, PORTI_4, input, X)," & "371 (BC_1, PORTI_4, output3, X, 372, 0, Z)," & "372 (BC_1, *, control, 0)," & "373 (BC_2, PORTI_3, input, X)," & "374 (BC_1, PORTI_3, output3, X, 375, 0, Z)," & "375 (BC_1, *, control, 0)," & "376 (BC_2, PORTI_2, input, X)," & "377 (BC_1, PORTI_2, output3, X, 378, 0, Z)," & "378 (BC_1, *, control, 0)," & "379 (BC_2, PORTI_1, input, X)," & -- num cell port func safe [ccell dis rslt] "380 (BC_1, PORTI_1, output3, X, 381, 0, Z)," & "381 (BC_1, *, control, 0)," & "382 (BC_2, PORTI_0, input, X)," & "383 (BC_1, PORTI_0, output3, X, 384, 0, Z)," & "384 (BC_1, *, control, 0)," & "385 (BC_2, PORTH_13, input, X)," & "386 (BC_1, PORTH_13, output3, X, 387, 0, Z)," & "387 (BC_1, *, control, 0)," & "388 (BC_2, PORTH_12, input, X)," & "389 (BC_1, PORTH_12, output3, X, 390, 0, Z)," & "390 (BC_1, *, control, 0)," & "391 (BC_2, PORTH_11, input, X)," & "392 (BC_1, PORTH_11, output3, X, 393, 0, Z)," & "393 (BC_1, *, control, 0)," & "394 (BC_2, PORTH_10, input, X)," & "395 (BC_1, PORTH_10, output3, X, 396, 0, Z)," & "396 (BC_1, *, control, 0)," & "397 (BC_2, PORTH_9, input, X)," & "398 (BC_1, PORTH_9, output3, X, 399, 0, Z)," & "399 (BC_1, *, control, 0)," & -- num cell port func safe [ccell dis rslt] "400 (BC_2, PORTH_8, input, X)," & "401 (BC_1, PORTH_8, output3, X, 402, 0, Z)," & "402 (BC_1, *, control, 0)," & "403 (BC_2, ADDR3, input, X)," & "404 (BC_1, ADDR3, output3, X, 405, 0, Z)," & "405 (BC_1, *, control, 0)," & "406 (BC_2, ADDR2, input, X)," & "407 (BC_1, ADDR2, output3, X, 408, 0, Z)," & "408 (BC_1, *, control, 0)," & "409 (BC_2, ADDR1, input, X)," & "410 (BC_1, ADDR1, output3, X, 411, 0, Z)," & "411 (BC_1, *, control, 0)," & "412 (BC_2, PORTH_6, input, X)," & "413 (BC_1, PORTH_6, output3, X, 414, 0, Z)," & "414 (BC_1, *, control, 0)," & "415 (BC_2, MFS, input, X)," & "416 (BC_1, MFS, output3, X, 417, 0, Z)," & "417 (BC_1, *, control, 0)," & "418 (BC_2, PORTH_5, input, X)," & "419 (BC_1, PORTH_5, output3, X, 420, 0, Z)," & -- num cell port func safe [ccell dis rslt] "420 (BC_1, *, control, 0)," & "421 (BC_2, PORTH_7, input, X)," & "422 (BC_1, PORTH_7, output3, X, 423, 0, Z)," & "423 (BC_1, *, control, 0)," & "424 (BC_2, PORTC_4, input, X)," & "425 (BC_1, PORTC_4, output3, X, 426, 0, Z)," & "426 (BC_1, *, control, 0)," & "427 (BC_2, PORTC_5, input, X)," & "428 (BC_1, PORTC_5, output3, X, 429, 0, Z)," & "429 (BC_1, *, control, 0)," & "430 (BC_2, PORTC_6, input, X)," & "431 (BC_1, PORTC_6, output3, X, 432, 0, Z)," & "432 (BC_1, *, control, 0)," & "433 (BC_2, PORTC_7, input, X)," & "434 (BC_1, PORTC_7, output3, X, 435, 0, Z)," & "435 (BC_1, *, control, 0)," & "436 (BC_2, PORTC_0, input, X)," & "437 (BC_1, PORTC_0, output3, X, 438, 0, Z)," & "438 (BC_1, *, control, 0)," & "439 (BC_2, PORTC_1, input, X)," & -- num cell port func safe [ccell dis rslt] "440 (BC_1, PORTC_1, output3, X, 441, 0, Z)," & "441 (BC_1, *, control, 0)," & "442 (BC_2, PORTC_2, input, X)," & "443 (BC_1, PORTC_2, output3, X, 444, 0, Z)," & "444 (BC_1, *, control, 0)," & "445 (BC_2, PORTC_3, input, X)," & "446 (BC_1, PORTC_3, output3, X, 447, 0, Z)," & "447 (BC_1, *, control, 0)," & "448 (BC_2, PORTG_0, input, X)," & "449 (BC_1, PORTG_0, output3, X, 450, 0, Z)," & "450 (BC_1, *, control, 0)," & "451 (BC_2, PORTG_1, input, X)," & "452 (BC_1, PORTG_1, output3, X, 453, 0, Z)," & "453 (BC_1, *, control, 0)," & "454 (BC_2, PORTG_2, input, X)," & "455 (BC_1, PORTG_2, output3, X, 456, 0, Z)," & "456 (BC_1, *, control, 0)," & "457 (BC_2, PORTF_0, input, X)," & "458 (BC_1, PORTF_0, output3, X, 459, 0, Z)," & "459 (BC_1, *, control, 0)," & -- num cell port func safe [ccell dis rslt] "460 (BC_2, PORTF_1, input, X)," & "461 (BC_1, PORTF_1, output3, X, 462, 0, Z)," & "462 (BC_1, *, control, 0)," & "463 (BC_2, PORTF_2, input, X)," & "464 (BC_1, PORTF_2, output3, X, 465, 0, Z)," & "465 (BC_1, *, control, 0)," & "466 (BC_2, PORTF_3, input, X)," & "467 (BC_1, PORTF_3, output3, X, 468, 0, Z)," & "468 (BC_1, *, control, 0)," & "469 (BC_2, PORTF_4, input, X)," & "470 (BC_1, PORTF_4, output3, X, 471, 0, Z)," & "471 (BC_1, *, control, 0)," & "472 (BC_2, PORTF_5, input, X)," & "473 (BC_1, PORTF_5, output3, X, 474, 0, Z)," & "474 (BC_1, *, control, 0)," & "475 (BC_2, PORTF_6, input, X)," & "476 (BC_1, PORTF_6, output3, X, 477, 0, Z)," & "477 (BC_1, *, control, 0)," & "478 (BC_2, PORTF_7, input, X)," & "479 (BC_1, PORTF_7, output3, X, 480, 0, Z)," & -- num cell port func safe [ccell dis rslt] "480 (BC_1, *, control, 0)," & "481 (BC_2, PORTF_8, input, X)," & "482 (BC_1, PORTF_8, output3, X, 483, 0, Z)," & "483 (BC_1, *, control, 0)," & "484 (BC_2, PORTF_9, input, X)," & "485 (BC_1, PORTF_9, output3, X, 486, 0, Z)," & "486 (BC_1, *, control, 0)," & "487 (BC_2, PORTF_10, input, X)," & "488 (BC_1, PORTF_10, output3, X, 489, 0, Z)," & "489 (BC_1, *, control, 0)," & "490 (BC_2, PORTF_11, input, X)," & "491 (BC_1, PORTF_11, output3, X, 492, 0, Z)," & "492 (BC_1, *, control, 0)," & "493 (BC_2, PORTF_12, input, X)," & "494 (BC_1, PORTF_12, output3, X, 495, 0, Z)," & "495 (BC_1, *, control, 0)," & "496 (BC_2, PORTF_13, input, X)," & "497 (BC_1, PORTF_13, output3, X, 498, 0, Z)," & "498 (BC_1, *, control, 0)," & "499 (BC_2, PORTF_14, input, X)," & -- num cell port func safe [ccell dis rslt] "500 (BC_1, PORTF_14, output3, X, 501, 0, Z)," & "501 (BC_1, *, control, 0)," & "502 (BC_2, PORTF_15, input, X)," & "503 (BC_1, PORTF_15, output3, X, 504, 0, Z)," & "504 (BC_1, *, control, 0)," & "505 (BC_2, PORTG_3, input, X)," & "506 (BC_1, PORTG_3, output3, X, 507, 0, Z)," & "507 (BC_1, *, control, 0)," & "508 (BC_2, PORTG_4, input, X)," & "509 (BC_1, PORTG_4, output3, X, 510, 0, Z)," & "510 (BC_1, *, control, 0)," & "511 (BC_2, PORTE_11, input, X)," & "512 (BC_1, PORTE_11, output3, X, 513, 0, Z)," & "513 (BC_1, *, control, 0)," & "514 (BC_2, PORTE_12, input, X)," & "515 (BC_1, PORTE_12, output3, X, 516, 0, Z)," & "516 (BC_1, *, control, 0)," & "517 (BC_2, PORTE_13, input, X)," & "518 (BC_1, PORTE_13, output3, X, 519, 0, Z)," & "519 (BC_1, *, control, 0)," & -- num cell port func safe [ccell dis rslt] "520 (BC_2, PORTD_0, input, X)," & "521 (BC_1, PORTD_0, output3, X, 522, 0, Z)," & "522 (BC_1, *, control, 0)," & "523 (BC_2, PORTD_1, input, X)," & "524 (BC_1, PORTD_1, output3, X, 525, 0, Z)," & "525 (BC_1, *, control, 0)," & "526 (BC_2, PORTD_2, input, X)," & "527 (BC_1, PORTD_2, output3, X, 528, 0, Z)," & "528 (BC_1, *, control, 0)," & "529 (BC_2, PORTD_3, input, X)," & "530 (BC_1, PORTD_3, output3, X, 531, 0, Z)," & "531 (BC_1, *, control, 0)," & "532 (BC_2, PORTD_4, input, X)," & "533 (BC_1, PORTD_4, output3, X, 534, 0, Z)," & "534 (BC_1, *, control, 0)," & "535 (BC_2, PORTD_5, input, X)," & "536 (BC_1, PORTD_5, output3, X, 537, 0, Z)," & "537 (BC_1, *, control, 0)," & "538 (BC_2, PORTD_6, input, X)," & "539 (BC_1, PORTD_6, output3, X, 540, 0, Z)," & -- num cell port func safe [ccell dis rslt] "540 (BC_1, *, control, 0)," & "541 (BC_2, PORTD_7, input, X)," & "542 (BC_1, PORTD_7, output3, X, 543, 0, Z)," & "543 (BC_1, *, control, 0)," & "544 (BC_2, PORTD_8, input, X)," & "545 (BC_1, PORTD_8, output3, X, 546, 0, Z)," & "546 (BC_1, *, control, 0)," & "547 (BC_2, PORTD_9, input, X)," & "548 (BC_1, PORTD_9, output3, X, 549, 0, Z)," & "549 (BC_1, *, control, 0)," & "550 (BC_2, PORTD_10, input, X)," & "551 (BC_1, PORTD_10, output3, X, 552, 0, Z)," & "552 (BC_1, *, control, 0)," & "553 (BC_2, PORTD_11, input, X)," & "554 (BC_1, PORTD_11, output3, X, 555, 0, Z)," & "555 (BC_1, *, control, 0)," & "556 (BC_2, PORTD_12, input, X)," & "557 (BC_1, PORTD_12, output3, X, 558, 0, Z)," & "558 (BC_1, *, control, 0)," & "559 (BC_2, PORTD_13, input, X)," & -- num cell port func safe [ccell dis rslt] "560 (BC_1, PORTD_13, output3, X, 561, 0, Z)," & "561 (BC_1, *, control, 0)," & "562 (BC_2, PORTD_15, input, X)," & "563 (BC_1, PORTD_15, output3, X, 564, 0, Z)," & "564 (BC_1, *, control, 0)," & "565 (BC_2, PORTD_14, input, X)," & "566 (BC_1, PORTD_14, output3, X, 567, 0, Z)," & "567 (BC_1, *, control, 0)," & "568 (BC_2, BMODE0, input, X)," & "569 (BC_2, BMODE1, input, X)," & "570 (BC_2, BMODE2, input, X)," & "571 (BC_2, BMODE3, input, X)," & "572 (BC_2, *, internal, 0)," & "573 (BC_2, PORTB_3, input, X)," & "574 (BC_1, PORTB_3, output3, X, 575, 0, Z)," & "575 (BC_1, *, control, 0)," & "576 (BC_2, PORTB_2, input, X)," & "577 (BC_1, PORTB_2, output3, X, 578, 0, Z)," & "578 (BC_1, *, control, 0)," & "579 (BC_2, PORTB_0, input, X)," & -- num cell port func safe [ccell dis rslt] "580 (BC_1, PORTB_0, output2, 1, 580, 1, WEAK1)," & "581 (BC_1, *, internal, 1)," & "582 (BC_2, PORTB_1, input, X)," & "583 (BC_1, PORTB_1, output2, 1, 583, 1, WEAK1)," & "584 (BC_1, *, internal, 1)," & "585 (BC_2, PORTB_7, input, X)," & "586 (BC_1, PORTB_7, output3, X, 587, 0, Z)," & "587 (BC_1, *, control, 0)," & "588 (BC_2, PORTB_6, input, X)," & "589 (BC_1, PORTB_6, output3, X, 590, 0, Z)," & "590 (BC_1, *, control, 0)," & "591 (BC_2, PORTB_5, input, X)," & "592 (BC_1, PORTB_5, output3, X, 593, 0, Z)," & "593 (BC_1, *, control, 0)," & "594 (BC_2, PORTB_4, input, X)," & "595 (BC_1, PORTB_4, output3, X, 596, 0, Z)," & "596 (BC_1, *, control, 0)," & "597 (BC_2, PORTB_11, input, X)," & "598 (BC_1, PORTB_11, output3, X, 599, 0, Z)," & "599 (BC_1, *, control, 0)," & -- num cell port func safe [ccell dis rslt] "600 (BC_2, PORTB_10, input, X)," & "601 (BC_1, PORTB_10, output3, X, 602, 0, Z)," & "602 (BC_1, *, control, 0)," & "603 (BC_2, PORTB_9, input, X)," & "604 (BC_1, PORTB_9, output3, X, 605, 0, Z)," & "605 (BC_1, *, control, 0)," & "606 (BC_2, PORTB_8, input, X)," & "607 (BC_1, PORTB_8, output3, X, 608, 0, Z)," & "608 (BC_1, *, control, 0)," & "609 (BC_2, PORTB_14, input, X)," & "610 (BC_1, PORTB_14, output3, X, 611, 0, Z)," & "611 (BC_1, *, control, 0)," & "612 (BC_2, PORTB_13, input, X)," & "613 (BC_1, PORTB_13, output3, X, 614, 0, Z)," & "614 (BC_1, *, control, 0)," & "615 (BC_2, PORTB_12, input, X)," & "616 (BC_1, PORTB_12, output3, X, 617, 0, Z)," & "617 (BC_1, *, control, 0)," & "618 (BC_2, PORTA_15, input, X)," & "619 (BC_1, PORTA_15, output3, X, 620, 0, Z)," & -- num cell port func safe [ccell dis rslt] "620 (BC_1, *, control, 0)," & "621 (BC_2, PORTA_14, input, X)," & "622 (BC_1, PORTA_14, output3, X, 623, 0, Z)," & "623 (BC_1, *, control, 0)," & "624 (BC_2, PORTA_13, input, X)," & "625 (BC_1, PORTA_13, output3, X, 626, 0, Z)," & "626 (BC_1, *, control, 0)," & "627 (BC_2, PORTA_12, input, X)," & "628 (BC_1, PORTA_12, output3, X, 629, 0, Z)," & "629 (BC_1, *, control, 0)," & "630 (BC_2, PORTA_11, input, X)," & "631 (BC_1, PORTA_11, output3, X, 632, 0, Z)," & "632 (BC_1, *, control, 0)," & "633 (BC_2, PORTA_10, input, X)," & "634 (BC_1, PORTA_10, output3, X, 635, 0, Z)," & "635 (BC_1, *, control, 0)"; end ADSP_BF549;