Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedWed Aug 12 17:48:53 2015 product_versionVivado v2014.3 (64-bit)
build_version1034051 os_platformLIN64
registration_id175672585_209872009_210561390_407 tool_flowVivado
betaFALSE route_designTRUE
target_familykintex7 target_devicexc7k325t
target_packageffg900 target_speed-2
random_id0fa9de48f4d25a99b9de3a318262bbe1 project_id4ba8c593f7764c9aa4820a63eb573b53
project_iteration0

user_environment
os_nameRedHatEnterpriseClient os_releaseRed Hat Enterprise Linux Client release 5.8 (Tikanga)
cpu_nameIntel(R) Core(TM) i7 CPU X 990 @ 3.47GHz cpu_speed1600.000 MHz
total_processors1 system_ram25.000 GB

vivado_usage
project_data
srcsetcount=7 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=6 totalimplruns=6

unisim_transformation
pre_unisim_transformation
bufg=10 bufgctrl=1 carry4=391 fdce=704
fdpe=21 fdre=4248 fdse=104 gnd=308
gtxe2_channel=4 gtxe2_common=1 ibuf=21 ibufds=2
ibufds_gte2=1 iobuf=9 lut1=767 lut2=715
lut3=541 lut4=834 lut5=1163 lut6=2500
muxf7=32 muxf8=8 obuf=20 obufds=2
obuft=1 plle2_adv=3 ramb36e1=132 srl16e=53
srlc32e=28 vcc=165
post_unisim_transformation
bufg=10 bufgctrl=1 carry4=391 fdce=704
fdpe=21 fdre=4248 fdse=104 gnd=308
gtxe2_channel=4 gtxe2_common=1 ibuf=30 ibufds=2
ibufds_gte2=1 lut1=767 lut2=715 lut3=541
lut4=834 lut5=1163 lut6=2500 muxf7=32
muxf8=8 obuf=20 obufds=2 obuft=10
plle2_adv=3 ramb36e1=132 srl16e=53 srlc32e=28
vcc=165

placer
usage
lut=5025 ff=4974 bram36=132 bram18=0
ctrls=154 dsp=0 iob=49 bufg=0
global_clocks=9 pll=3 bufr=0 nets=13962
movable_instances=12091 pins=98529 bogomips=6949 effort=2
threads=8 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=34.050000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=4974 srls_augmented=0
srls_newly_gated=0 srls_total=81 bram_ports_augmented=0 bram_ports_newly_gated=4
bram_ports_total=264 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
blk_mem_gen_v8_2/1
iptotal=1 x_ipproduct=Vivado 2014.3 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=2 x_iplanguage=VERILOG
c_family=kintex7 c_xdevicefamily=kintex7 c_elaboration_dir=./ c_interface_type=0
c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=0 c_enable_32bit_address=0
c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4 c_mem_type=1
c_byte_size=9 c_algorithm=0 c_prim_type=4 c_load_init_file=0
c_init_file_name=no_coe_file_loaded c_init_file=blk_mem_gen_gcp.mem c_use_default_data=0 c_default_data=0
c_has_rsta=0 c_rst_priority_a=CE c_rstram_a=0 c_inita_val=0
c_has_ena=0 c_has_regcea=0 c_use_byte_wea=0 c_wea_width=1
c_write_mode_a=WRITE_FIRST c_write_width_a=128 c_read_width_a=128 c_write_depth_a=32768
c_read_depth_a=32768 c_addra_width=15 c_has_rstb=0 c_rst_priority_b=CE
c_rstram_b=0 c_initb_val=0 c_has_enb=0 c_has_regceb=0
c_use_byte_web=0 c_web_width=1 c_write_mode_b=WRITE_FIRST c_write_width_b=8
c_read_width_b=8 c_write_depth_b=524288 c_read_depth_b=524288 c_addrb_width=19
c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0
c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_use_softecc=0
c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0 c_sim_collision_check=ALL
c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0 c_disable_warn_bhv_range=0
c_count_36k_bram=128 c_count_18k_bram=0 c_est_power_summary=Estimated Power for IP _ 20.009202 mW
clk_wiz_v5_1/1
iptotal=1 component_name=clk_wiz_rx_aclk_2 use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=PLL num_out_clk=3
clkin1_period=6.4 clkin2_period=10.0 use_power_down=false use_reset=true
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false
clk_wiz_v5_1/2
iptotal=1 component_name=clk_wiz_rx_fclk use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=PLL num_out_clk=1
clkin1_period=16.667 clkin2_period=10.0 use_power_down=false use_reset=true
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false
clk_wiz_v5_1/3
iptotal=1 component_name=clk_wiz_rx_sysclk use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=PLL num_out_clk=1
clkin1_period=5.0 clkin2_period=10.0 use_power_down=false use_reset=true
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false
gtwizard_v3_4/1
iptotal=1 protocol_file=JESD204
jesd204_phy_v1_0/1
iptotal=1 x_ipproduct=Vivado 2014.3 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=jesd204_phy x_ipversion=1.0 x_ipcorerevision=0 x_iplanguage=VERILOG
c_component_name=jd204bv6p0l4sc0_phy c_family=kintex7 c_lanes=4 c_speedgrade=-2
c_supportlevel=1 c_transceivercontrol=true c_sub_core_name=jd204bv6p0l4sc0_phy_gt c_gt_line_rate=6.25
c_gt_refclk_freq=156.250 c_drpclk_freq=156.25 c_pll_selection=0 c_rx_gt_line_rate=6.25
c_rx_gt_refclk_freq=156.250 c_rx_pll_selection=0 c_qpll_fbdiv=40 c_qpll_refclkdiv=1
c_pll0_fbdiv=1 c_pll0_fbdiv_45=4 c_pll0_refclkdiv=1 c_pll1_fbdiv=1
c_pll1_fbdiv_45=4 c_pll1_refclkdiv=1
jesd204_v6_0/1
iptotal=1 x_ipproduct=Vivado 2014.3 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=jesd204 x_ipversion=6.0 x_ipcorerevision=0 x_iplanguage=VERILOG
x_iplicense=jesd204@2014.10(bought) c_elaboration_transient_dir=0 c_component_name=jd204bv6p0l4sc0 c_family=kintex7
c_node_is_transmit=0 c_lanes=4 c_use_bram=1 c_speedgrade=-2
c_lmfc_buffer_size=6 c_supportlevel=1 c_use_rpat=false c_use_jspat=false
c_transceivercontrol=false c_sub_core_name=jd204bv6p0l4sc0_phy c_gt_line_rate=6.25 c_gt_refclk_freq=156.250
c_drpclk_freq=156.25 c_sysref_sampling_edge=0 c_pll_selection=0 c_global_clk_sel=false
c_default_scr=0 c_default_f=2 c_default_k=10 c_default_sysref_always=0
c_default_sysref_required=1

report_utilization
slice_logic
slice_luts_used=5024 slice_luts_fixed=0 slice_luts_available=203800 slice_luts_util_percentage=2.46
lut_as_logic_used=4943 lut_as_logic_fixed=0 lut_as_logic_available=203800 lut_as_logic_util_percentage=2.42
lut_as_memory_used=81 lut_as_memory_fixed=0 lut_as_memory_available=64000 lut_as_memory_util_percentage=0.12
lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0 lut_as_shift_register_used=81 lut_as_shift_register_fixed=0
slice_registers_used=4974 slice_registers_fixed=0 slice_registers_available=407600 slice_registers_util_percentage=1.22
register_as_flip_flop_used=4974 register_as_flip_flop_fixed=0 register_as_flip_flop_available=407600 register_as_flip_flop_util_percentage=1.22
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=407600 register_as_latch_util_percentage=0.00
f7_muxes_used=32 f7_muxes_fixed=0 f7_muxes_available=101900 f7_muxes_util_percentage=0.03
f8_muxes_used=8 f8_muxes_fixed=0 f8_muxes_available=50950 f8_muxes_util_percentage=0.01
slice_used=2139 slice_fixed=0 slice_available=50950 slice_util_percentage=4.19
slicel_used=1361 slicel_fixed=0 slicem_used=778 slicem_fixed=0
lut_as_logic_used=4943 lut_as_logic_fixed=0 lut_as_logic_available=203800 lut_as_logic_util_percentage=2.42
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=4097 using_o6_output_only_fixed=
using_o5_and_o6_used=846 using_o5_and_o6_fixed= lut_as_memory_used=81 lut_as_memory_fixed=0
lut_as_memory_available=64000 lut_as_memory_util_percentage=0.12 lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=81 lut_as_shift_register_fixed=0 using_o5_output_only_used=0 using_o5_output_only_fixed=
using_o6_output_only_used=81 using_o6_output_only_fixed= using_o5_and_o6_used=0 using_o5_and_o6_fixed=
lut_flip_flop_pairs_used=6523 lut_flip_flop_pairs_fixed=0 lut_flip_flop_pairs_available=203800 lut_flip_flop_pairs_util_percentage=3.20
fully_used_lut_ff_pairs_used=2720 fully_used_lut_ff_pairs_fixed= lut_ff_pairs_with_unused_lut_used=1499 lut_ff_pairs_with_unused_lut_fixed=
lut_ff_pairs_with_unused_flip_flop_used=2304 lut_ff_pairs_with_unused_flip_flop_fixed= unique_control_sets_used=154 minimum_number_of_registers_lost_to_control_set_restriction_used=466(Lost)
memory
block_ram_tile_used=132 block_ram_tile_fixed=0 block_ram_tile_available=445 block_ram_tile_util_percentage=29.66
ramb36_fifo*_used=132 ramb36_fifo*_fixed=0 ramb36_fifo*_available=445 ramb36_fifo*_util_percentage=29.66
ramb36e1_only_used=132 ramb18_used=0 ramb18_fixed=0 ramb18_available=890
ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_fixed=0 dsps_available=840 dsps_util_percentage=0.00
clocking
bufgctrl_used=9 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=28.12
bufio_used=0 bufio_fixed=0 bufio_available=40 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_fixed=0 mmcme2_adv_available=10 mmcme2_adv_util_percentage=0.00
plle2_adv_used=3 plle2_adv_fixed=0 plle2_adv_available=10 plle2_adv_util_percentage=30.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=20 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=168 bufhce_util_percentage=0.00
bufr_used=0 bufr_fixed=0 bufr_available=40 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_fixed=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=4191 fdre_functional_category=Flop & Latch lut6_used=2457 lut6_functional_category=LUT
lut5_used=1178 lut5_functional_category=LUT lut4_used=807 lut4_functional_category=LUT
lut2_used=695 lut2_functional_category=LUT fdce_used=658 fdce_functional_category=Flop & Latch
lut3_used=531 lut3_functional_category=LUT carry4_used=391 carry4_functional_category=CarryLogic
ramb36e1_used=132 ramb36e1_functional_category=Block Memory lut1_used=121 lut1_functional_category=LUT
fdse_used=104 fdse_functional_category=Flop & Latch srl16e_used=53 srl16e_functional_category=Distributed Memory
muxf7_used=32 muxf7_functional_category=MuxFx ibuf_used=30 ibuf_functional_category=IO
srlc32e_used=28 srlc32e_functional_category=Distributed Memory fdpe_used=21 fdpe_functional_category=Flop & Latch
obuf_used=20 obuf_functional_category=IO obuft_used=10 obuft_functional_category=IO
muxf8_used=8 muxf8_functional_category=MuxFx bufg_used=8 bufg_functional_category=Clock
gtxe2_channel_used=4 gtxe2_channel_functional_category=IO plle2_adv_used=3 plle2_adv_functional_category=Clock
obufds_used=2 obufds_functional_category=IO ibufds_used=2 ibufds_functional_category=IO
ibufds_gte2_used=1 ibufds_gte2_functional_category=IO gtxe2_common_used=1 gtxe2_common_functional_category=IO
bufgctrl_used=1 bufgctrl_functional_category=Clock
io_standard
lvds=0 sstl15_dci=0 sstl18_ii_dci=0 sstl18_i_dci=0
sstl12=0 sstl135_r=0 sstl135=0 sstl15_r=0
sstl15=0 sstl18_ii=0 sstl18_i=0 hstl_i_12=0
hstl_ii_t_dci_18=0 hstl_ii_dci_18=0 hstl_i_dci_18=0 hstl_ii_18=0
hstl_i_18=0 hstl_ii_t_dci=0 hstl_ii_dci=0 hstl_i_dci=0
lvcmos12=0 lvcmos18=0 lvcmos25=1 lvcmos15=1
sstl18_ii_t_dci=0 lvttl=0 mini_lvds_25=0 hstl_i=0
lvcmos33=0 hsul_12=0 lvdci_18=0 lvdci_15=0
hsul_12_dci=0 hslvdci_18=0 hslvdci_15=0 lvdci_dv2_18=0
lvdci_dv2_15=0 hstl_ii=0 sstl15_t_dci=0 sstl135_dci=0
sstl135_t_dci=0 sstl12_dci=0 sstl12_t_dci=0 diff_hstl_i=0
diff_hstl_ii=0 diff_hstl_i_18=0 diff_hstl_ii_18=1 diff_sstl18_i=0
diff_sstl18_ii=0 diff_sstl15=1 diff_sstl15_r=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl12=0 diff_hsul_12=0 diff_hstl_i_dci=0
diff_hstl_ii_dci=0 diff_hstl_ii_t_dci=0 diff_hstl_i_dci_18=0 diff_hstl_ii_dci_18=0
diff_hstl_ii_t_dci_18=0 diff_sstl18_i_dci=0 diff_sstl18_ii_dci=0 diff_sstl18_ii_t_dci=0
diff_sstl15_dci=0 diff_sstl15_t_dci=0 diff_sstl135_dci=0 diff_sstl135_t_dci=0
diff_sstl12_dci=0 diff_sstl12_t_dci=0 diff_hsul_12_dci=0 pci33_3=0
mobile_ddr=0 diff_mobile_ddr=0 blvds_25=0 lvds_25=1
rsds_25=0 tmds_33=0 ppds_25=0

router
usage
lut=5526 ff=4974 bram36=132 bram18=0
ctrls=154 dsp=0 iob=49 bufg=0
global_clocks=9 pll=3 bufr=0 nets=13962
movable_instances=12091 pins=98529 bogomips=6949 high_fanout_nets=13
effort=2 threads=8 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=20539026 actual_expansions=22243778 router_runtime=99.500000

synthesis
command_line_options
-part=xc7k325tffg900-2 -name=default::[not_specified] -top=jd204bv6p0l4sc0_example_design -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-bufg=default::12 -fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default
-fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:00:27s memory_peak=1391.695MB memory_gain=491.609MB

xsim
command_line_options
-sim_mode=post-implementation -sim_type=timing