DC2100A  1.2.0
Bi-Directional Cell Balancer Using the LTC3300-1 and the LTC6804-2
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LTC6804-2_Registers.h
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1 /*
2  Linear Technology DC2100A Demonstration Board.
3  Driver Registers for LTC6804-2 Multicell Battery Monitors.
4  All datasheet references in this file refer to Linear Technology Corp. document 680412fa.pdf.
5 
6  @verbatim
7  The LTC6804 is a 3rd generation multicell battery stack
8  monitor that measures up to 12 series connected battery
9  cells with a total measurement error of less than 1.2mV. The
10  cell measurement range of 0V to 5V makes the LTC6804
11  suitable for most battery chemistries. All 12 cell voltages
12  can be captured in 290us, and lower data acquisition rates
13  can be selected for high noise reduction.
14  Multiple LTC6804 devices can be connected in series,
15  permitting simultaneous cell monitoring of long, high voltage
16  battery strings. Each LTC6804 has an isoSPI interface
17  for high speed, RF-immune, local area communications.
18  Using the LTC6804-2, multiple devices are connected in
19  a daisy-chain with one host processor connection for all
20  devices. Using the LTC6804-2, multiple devices are connected
21  in parallel to the host processor, with each device
22  individually addressed.
23  Additional features include passive balancing for each cell,
24  an onboard 5V regulator, and 5 general purpose I/O lines.
25  In sleep mode, current consumption is reduced to 4uA.
26  The LTC6804 can be powered directly from the battery,
27  or from an isolated supply.
28  @endverbatim
29 
30  http://www.linear.com/product/LTC6804
31 
32  http://www.linear.com/product/LTC6804#demoboards
33 
34  REVISION HISTORY
35  $Revision: 556 $
36  $Date: 2014-08-08 11:34:04 -0400 (Fri, 08 Aug 2014) $
37 
38  Copyright (c) 2013, Linear Technology Corp.(LTC)
39  All rights reserved.
40 
41  Redistribution and use in source and binary forms, with or without
42  modification, are permitted provided that the following conditions are met:
43 
44  1. Redistributions of source code must retain the above copyright notice, this
45  list of conditions and the following disclaimer.
46  2. Redistributions in binary form must reproduce the above copyright notice,
47  this list of conditions and the following disclaimer in the documentation
48  and/or other materials provided with the distribution.
49 
50  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
51  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
52  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
53  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
54  ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
55  (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
56  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
57  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
59  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60 
61  The views and conclusions contained in the software and documentation are those
62  of the authors and should not be interpreted as representing official policies,
63  either expressed or implied, of Linear Technology Corp.
64 
65 */
66 
67 /*! @file
68  @ingroup LTC6804-2
69  Driver Registers for LTC6804-2 Multicell Battery Monitors.
70 */
71 
72 #ifndef __LTC6804_REGISTERS_H__
73 #define __LTC6804_REGISTERS_H__
74 
75 //-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
76 // Includes
77 //-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
78 #include "Typedefs.h"
79 #include "DC2100A.h"
80 
81 //-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
82 // Definitions
83 //-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
84 
85 // LTC6803 Command Codes are addressed, defined by datasheet Table 32 and Table 33
86 #define LTC6804_COMMAND_CODE_BROADCAST_ADDRESS 0x00 // Address used for an LTC6804 command to be broadcast to all boards
87 #define LTC6804_COMMAND_CODE_ADDRESSED_BIT 0x10 // Bit set in address used for an LTC6804 command to be addressed to one board
88 #define LTC6804_COMMAND_CODE_ADDRESS_MASK 0x0F
89 #define LTC6804_COMMAND_CODE_ADDRESS(command_code, address) ((command_code & 0x7FF) | ((int16)(address & 0x1F) << 11))
90 
91 // LTC6803 Command Codes Base Address, as defined by datasheet Table 34
92 #define LTC6804_COMMAND_CODE_BASE_WRCFG 0x001 // Write Configuration Register Group
93 #define LTC6804_COMMAND_CODE_BASE_RDCFG 0x002 // Read Configuration Register Group
94 #define LTC6804_COMMAND_CODE_BASE_RDCVA 0x004 // Read Cell Voltage Register Group A
95 #define LTC6804_COMMAND_CODE_BASE_RDCVB 0x006 // Read Cell Voltage Register Group B
96 #define LTC6804_COMMAND_CODE_BASE_RDCVC 0x008 // Read Cell Voltage Register Group C
97 #define LTC6804_COMMAND_CODE_BASE_RDCVD 0x00A // Read Cell Voltage Register Group D
98 #define LTC6804_COMMAND_CODE_BASE_RDAUXA 0x00C // Read Auxiliary Register Group A
99 #define LTC6804_COMMAND_CODE_BASE_RDAUXB 0x00E // Read Auxiliary Register Group B
100 #define LTC6804_COMMAND_CODE_BASE_RDSTATA 0x010 // Read Status Register Group A
101 #define LTC6804_COMMAND_CODE_BASE_RDSTATB 0x012 // Read Status Register Group B
102 #define LTC6804_COMMAND_CODE_BASE_ADCV 0x260 // Start Cell Voltage ADC Conversion and Poll Status
103 #define LTC6804_COMMAND_CODE_BASE_ADOW 0x228 // Start Open Wire ADC Conversion and Poll Status
104 #define LTC6804_COMMAND_CODE_BASE_CVST 0x207 // Start Self-Test Cell Voltage Conversion and Poll Status
105 #define LTC6804_COMMAND_CODE_BASE_ADAX 0x460 // Start GPIOs ADC Conversion and Poll Status
106 #define LTC6804_COMMAND_CODE_BASE_AXST 0x407 // Start Self-Test GPIOs Conversion and Poll Status
107 #define LTC6804_COMMAND_CODE_BASE_ADSTAT 0x468 // Start Status group ADC Conversion and Poll Status
108 #define LTC6804_COMMAND_CODE_BASE_STATST 0x40F // Start Self-Test Status group Conversion and Poll Status
109 #define LTC6804_COMMAND_CODE_BASE_ADCVAX 0x46F // Start Combined Cell Voltage and GPIO1, GPIO2 Conversion and Poll Status
110 #define LTC6804_COMMAND_CODE_BASE_CLRCELL 0x711 // Clear Cell Voltage Register Group
111 #define LTC6804_COMMAND_CODE_BASE_CLRAUX 0x712 // Clear Auxiliary Register Group
112 #define LTC6804_COMMAND_CODE_BASE_CLRSTAT 0x713 // Clear Status Register Group
113 #define LTC6804_COMMAND_CODE_BASE_PLADC 0x714 // Poll ADC Conversion Status
114 #define LTC6804_COMMAND_CODE_BASE_DIAGN 0x715 // Diagnose MUX and Poll Status
115 #define LTC6804_COMMAND_CODE_BASE_WRCOMM 0x721 // Write COMM Register Group
116 #define LTC6804_COMMAND_CODE_BASE_RDCOMM 0x722 // Read COMM Register Group
117 #define LTC6804_COMMAND_CODE_BASE_STCOMM 0x723 // Start I2C/SPI Communication
118 
119 // LTC6803 Command Codes with variable bits, as defined by datasheet Table 34 and Table 35
120 #define LTC6804_COMMAND_CODE_WRCFG(address) \
121  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_WRCFG, address)) // Write Configuration Register Group
122 #define LTC6804_COMMAND_CODE_RDCFG(address) \
123  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_RDCFG, address)) // Read Configuration Register Group
124 #define LTC6804_COMMAND_CODE_RDCVA(address) \
125  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_RDCVA, address)) // Read Cell Voltage Register Group A
126 #define LTC6804_COMMAND_CODE_RDCVB(address) \
127  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_RDCVB, address)) // Read Cell Voltage Register Group B
128 #define LTC6804_COMMAND_CODE_RDCVC(address) \
129  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_RDCVC, address)) // Read Cell Voltage Register Group C
130 #define LTC6804_COMMAND_CODE_RDCVD(address) \
131  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_RDCVD, address)) // Read Cell Voltage Register Group D
132 #define LTC6804_COMMAND_CODE_RDAUXA(address) \
133  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_RDAUXA, address)) // Read Auxiliary Register Group A
134 #define LTC6804_COMMAND_CODE_RDAUXB(address) \
135  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_RDAUXB, address)) // Read Auxiliary Register Group B
136 #define LTC6804_COMMAND_CODE_RDSTATA(address) \
137  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_RDSTATA, address)) // Read Status Register Group A
138 #define LTC6804_COMMAND_CODE_RDSTATB(address) \
139  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_RDSTATB, address)) // Read Status Register Group B
140 #define LTC6804_COMMAND_CODE_ADCV(address, md, dcp, ch) \
141  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_ADCV, address) + ((int16)(md & 0x3) << 7) + ((dcp & 0x1) << 4) + ((ch & 0x7) << 0)) // Start Cell Voltage ADC Conversion and Poll Status
142 #define LTC6804_COMMAND_CODE_ADOW(address, md, pup, dcp, ch)) \
143  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_ADOW, address) + ((int16)(md & 0x3) << 7) + ((pup & 0x1) << 4) + ((dcp & 0x1) << 4) + ((ch & 0x7) << 0)) // Start Open Wire ADC Conversion and Poll Status
144 #define LTC6804_COMMAND_CODE_CVST(address, md, st) \
145  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_CVST, address) + ((int16)(md & 0x3) << 7) + ((st & 0x3) << 5)) // Start Self-Test Cell Voltage Conversion and Poll Status
146 #define LTC6804_COMMAND_CODE_ADAX(address, md, chg) \
147  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_ADAX, address) + ((int16)(md & 0x3) << 7) + ((chg & 0x7) << 0)) // Start GPIOs ADC Conversion and Poll Status
148 #define LTC6804_COMMAND_CODE_AXST(address, md, st) \
149  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_AXST, address) + ((int16)(md & 0x3) << 7) + ((st & 0x3) << 5)) // Start Self-Test GPIOs Conversion and Poll Status
150 #define LTC6804_COMMAND_CODE_ADSTAT(address, md, chst) \
151  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_ADSTAT, address) + ((int16)(md & 0x3) << 7) + ((chst & 0x7) << 0)) // Start Status group ADC Conversion and Poll Status
152 #define LTC6804_COMMAND_CODE_STATST(address, md, st) \
153  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_STATST, address) + ((int16)(md & 0x3) << 7) + ((st & 0x3) << 5)) // Start Self-Test Status group Conversion and Poll Status
154 #define LTC6804_COMMAND_CODE_ADCVAX(address, md, dcp) \
155  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_ADCVAX, address) + ((int16)(md & 0x3) << 7) + ((dcp & 0x1) << 4)) // Start Combined Cell Voltage and GPIO1, GPIO2 Conversion and Poll Status
156 #define LTC6804_COMMAND_CODE_CLRCELL(address) \
157  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_CLRCELL, address)) // Clear Cell Voltage Register Group
158 #define LTC6804_COMMAND_CODE_CLRAUX(address) \
159  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_CLRAUX, address)) // Clear Auxiliary Register Group
160 #define LTC6804_COMMAND_CODE_CLRSTAT(address) \
161  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_CLRSTAT, address)) // Clear Status Register Group
162 #define LTC6804_COMMAND_CODE_PLADC(address) \
163  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_PLADC, address)) // Poll ADC Conversion Status
164 #define LTC6804_COMMAND_CODE_DIAGN(address) \
165  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_DIAGN, address)) // Diagnose MUX and Poll Status
166 #define LTC6804_COMMAND_CODE_WRCOMM(address) \
167  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_WRCOMM, address)) // Write COMM Register Group
168 #define LTC6804_COMMAND_CODE_RDCOMM(address) \
169  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_RDCOMM, address)) // Read COMM Register Group
170 #define LTC6804_COMMAND_CODE_STCOMM(address) \
171  (LTC6804_COMMAND_CODE_ADDRESS(LTC6804_COMMAND_CODE_BASE_STCOMM, address)) // Start I2C/SPI Communication
172 
173 // Configuration Register Group specified by datasheet Table 46: memory Bit Descriptions
174 // todo - some of this stuff could be dependent upon ADC bits, Number of GPIO, and Number of cells
175 #define LTC6804_CFGR0_ADCOPT(adcopt) (adcopt << 0) // ADC Mode Option Bit
176 #define LTC6804_CFGR0_ADCOPT_MASK LTC6804_CFGR0_ADCOPT(1) // ADCOPT: 0 -> Selects Modes 27kHz, 7kHz or 26Hz with MD[1:0] Bits in ADC Conversion Commands. 1 -> Selects Modes 14kHz, 3kHz or 2kHz with MD[1:0] Bits in ADC Conversion Commands.
177 #define LTC6804_CFGR0_SWTRD_MASK 0x02 // SWTEN Pin Status (Read Only): 1 -> SWTEN Pin at Logic 1 0 -> SWTEN Pin at Logic 0
178 #define LTC6804_CFGR0_REFON(ref_on) ((ref_on ? 1 : 0) << 2) // Reference Powered Up
179 #define LTC6804_CFGR0_REFON_MASK LTC6804_CFGR0_REFON(1) // 1 -> Reference Remains Powered Up Until Watchdog Timeout 0 -> Reference Shuts Down after Conversions
180 #define LTC6804_CFGR0_GPIOx(gpiox) ((gpiox & 0x1F) << 3) // GPIOx Pin Control
181 #define LTC6804_CFGR0_GPIOx_MASK LTC6804_CFGR0_GPIOx(0x1F) // Write: 0 -> GPIOx Pin Pull-Down ON; 1-> GPIOx Pin Pull-Down OFF Read: 0 -> GPIOx Pin at Logic 0; 1 -> GPIOx Pin at Logic 1
182 #define LTC6804_CFGR1_VUV(vuv) ((vuv & 0xFFF) << 0) // Undervoltage Comparison Voltage*
183 #define LTC6804_CFGR1_VUV_MASK LTC6804_CFGR1_VUV(0xFFF) // Comparison voltage = (VUV + 1) • 16 • 100µV Default: VUV = 0x000
184 #define LTC6804_CFGR2_VOV(vov) ((vov & 0xFFF) << 4) // Overvoltage Comparison Voltage*
185 #define LTC6804_CFGR2_VOV_MASK LTC6804_CFGR2_VOV(0xFFF) // Comparison voltage = VOV • 16 • 100µV Default: VOV = 0x000
186 #define LTC6804_CFGR4_DCCx(dccx) ((dccx & 0xFFF) << 0) // Discharge Cell x
187 #define LTC6804_CFGR4_DCCx_MASK LTC6804_CFGR4_DCCx(0xFFF) // "x = 1 to 12 1 -> Turn ON Shorting Switch for Cell x 0 -> Turn OFF Shorting Switch for Cell x (Default)"
188 #define LTC6804_CFGR5_DCTO(dcto) ((dcto & 0xF) << 4) // Discharge Time Out Value
189 #define LTC6804_CFGR5_DCTO_MASK LTC6804_CFGR5_DCTO(0xF) // todo - each value has a different code, with read and write being different. Enum really necessary?
190 
191 // Bit Definitions for adc options are specified by datasheet Table 46.
192 #define LTC6804_ADCOPT_0 0x0 // 0 -> Selects Modes 27kHz, 7kHz or 26Hz with MD[1:0] Bits in ADC Conversion Commands.
193 #define LTC6804_ADCOPT_1 0x1 // 1 -> Selects Modes 14kHz, 3kHz or 2kHz with MD[1:0] Bits in ADC Conversion Commands.
194 
195 // Bit Definitions for command codes are specified by datasheet Table 35.
196 #define LTC6804_MD_MODE_FAST 0x1 // ADC Mode: 27kHz (ADCOPT = 0), 14kHz (ADCOPT = 1)
197 #define LTC6804_MD_MODE_NORMAL 0x2 // ADC Mode: 7kHz (ADCOPT = 0), 3kHz (ADCOPT = 1)
198 #define LTC6804_MD_MODE_FILTERED 0x3 // ADC Mode: 26Hz (ADCOPT = 0), 2kHz (ADCOPT = 1)
199 
200 // Bit Definition for discharge permission is specified by datasheet Table 46.
201 #define LTC6804_DCP_DISCHARGE_NOT_PERMITTED 0 // Discharge Not Permitted
202 #define LTC6804_DCP_DISCHARGE_PERMITTED 1 // Discharge Permitted
203 
204 // Bit Definitions for COMM Register Group specified by datasheet Table 46: memory Bit Descriptions
205 #define LTC6804_ICOM_I2C_WRITE_START 0x6
206 #define LTC6804_ICOM_I2C_WRITE_STOP 0x1
207 #define LTC6804_ICOM_I2C_WRITE_BLANK 0x0
208 #define LTC6804_ICOM_I2C_WRITE_NO_TRANSMIT 0x7
209 #define LTC6804_ICOM_I2C_READ_START 0x6
210 #define LTC6804_ICOM_I2C_READ_STOP 0x1
211 #define LTC6804_ICOM_I2C_READ_SDA_LOW 0x0
212 #define LTC6804_ICOM_I2C_READ_SDA_HIGH 0x7
213 #define LTC6804_FCOM_WRITE_I2C_ACK 0x0
214 #define LTC6804_FCOM_WRITE_I2C_NACK 0x8
215 #define LTC6804_FCOM_WRITE_I2C_NACK_STOP 0x9
216 #define LTC6804_FCOM_READ_I2C_ACK_FROM_MASTER 0x0
217 #define LTC6804_FCOM_READ_I2C_ACK_FROM_SLAVE 0x7
218 #define LTC6804_FCOM_READ_I2C_NACK_FROM_SLAVE 0xF
219 #define LTC6804_FCOM_READ_I2C_ACK_FROM_SLAVE_STOP_FROM_MASTER 0x1
220 #define LTC6804_FCOM_READ_I2C_NACK_FROM_SLAVE_STOP_FROM_MASTER 0x9
221 
222 #define LTC6804_ICOM_SPI_WRITE_CSB_LOW 0x8
223 #define LTC6804_ICOM_SPI_WRITE_CSB_HIGH 0x9
224 #define LTC6804_ICOM_SPI_WRITE_NO_TRANSMIT 0xF
225 #define LTC6804_ICOM_SPI_READ 0x7
226 #define LTC6804_FCOM_SPI_WRITE_CSB_LOW 0x8
227 #define LTC6804_FCOM_SPI_WRITE_CSB_HIGH 0x9
228 #define LTC6804_FCOM_SPI_READ 0xF
229 
230 // COMM register data bytes must be set to 0xFF when reading.
231 #define LTC6804_COMM_READ_DUMMY 0xFF
232 
233 //-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
234 // Global Data
235 //-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
236 
237 //-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
238 // Global Prototypes
239 //-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
240 
241 #endif