Linduino  1.3.0
Linear Technology Arduino-Compatible Demonstration Board

LTC4155: Dual-Input Power Manager / 3.5A Li-Ion Battery Charger with I²C Control and USB OTG. More...

Detailed Description

LTC4155: Dual-Input Power Manager / 3.5A Li-Ion Battery Charger with I²C Control and USB OTG.

The LTC®4155 is a 15 watt I²C controlled power manager with PowerPath™ instant-
on operation, high efficiency switching battery charging and USB compatibility.
The LTC4155 seamlessly manages power distribution from two 5V sources, such as a
USB port and a wall adapter, to a single-cell rechargeable Lithium-Ion/Polymer
battery and a system load.

http://www.linear.com/product/LTC4155

http://www.linear.com/product/LTC4155#demoboards

Copyright 2018(c) Analog Devices, Inc.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  • Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  • The use of this software may or may not infringe the patent rights of one or more patent holders. This license does not release you from the requirement that you obtain separate licenses from these patent holders to use this software.
  • Use of the software either in source or binary form, must be run on or directly connected to an Analog Devices Inc. component.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Generated on: 2016-01-19

LTC4155 Register Map Definition Header

This file contains LTC4155 definitions for each command_code as well as each individual bit field for the case when a register contains multiple bit-packed fields smaller than the register width. Each bit field name is prepended with LTC4155_. Each bit field has individual definitions for its _SIZE, _OFFSET (LSB) and _MASK, as well as the three fields stored in a single 16-bit word for use with the access functions provided by LTC4155.c and LTC4155.h. In the case that the bit field contents represent an enumeration, _PRESET definitions exists to translate from human readable format to the encoded value. See LTC4155 Register Map Definitions for detailed descriptions of each bit field.

Definition in file LTC4155_reg_defs.h.

Go to the source code of this file.

Macros

#define LTC4155_ADDR_09   0x9
 LTC4155 I2C address in 7-bit format. More...
 
#define LTC4155_REG0_SUBADDR   0x00
 
#define LTC4155_REG0   (0 << 12 | (16 - 1) << 8 | LTC4155_REG0_SUBADDR)
 
#define LTC4155_DISABLE_INPUT_UVCL_SUBADDR   LTC4155_REG0_SUBADDR
 DISABLE_INPUT_UVCL More...
 
#define LTC4155_DISABLE_INPUT_UVCL_SIZE   1
 
#define LTC4155_DISABLE_INPUT_UVCL_OFFSET   7
 
#define LTC4155_DISABLE_INPUT_UVCL_MASK   0x80
 
#define LTC4155_DISABLE_INPUT_UVCL   (LTC4155_DISABLE_INPUT_UVCL_OFFSET << 12 | (LTC4155_DISABLE_INPUT_UVCL_SIZE - 1) << 8 | LTC4155_DISABLE_INPUT_UVCL_SUBADDR)
 
#define LTC4155_EN_BAT_CONDITIONER_SUBADDR   LTC4155_REG0_SUBADDR
 EN_BAT_CONDITIONER More...
 
#define LTC4155_EN_BAT_CONDITIONER_SIZE   1
 
#define LTC4155_EN_BAT_CONDITIONER_OFFSET   6
 
#define LTC4155_EN_BAT_CONDITIONER_MASK   0x40
 
#define LTC4155_EN_BAT_CONDITIONER   (LTC4155_EN_BAT_CONDITIONER_OFFSET << 12 | (LTC4155_EN_BAT_CONDITIONER_SIZE - 1) << 8 | LTC4155_EN_BAT_CONDITIONER_SUBADDR)
 
#define LTC4155_LOCKOUT_ID_PIN_SUBADDR   LTC4155_REG0_SUBADDR
 LOCKOUT_ID_PIN More...
 
#define LTC4155_LOCKOUT_ID_PIN_SIZE   1
 
#define LTC4155_LOCKOUT_ID_PIN_OFFSET   5
 
#define LTC4155_LOCKOUT_ID_PIN_MASK   0x20
 
#define LTC4155_LOCKOUT_ID_PIN   (LTC4155_LOCKOUT_ID_PIN_OFFSET << 12 | (LTC4155_LOCKOUT_ID_PIN_SIZE - 1) << 8 | LTC4155_LOCKOUT_ID_PIN_SUBADDR)
 
#define LTC4155_USBILIM_SUBADDR   LTC4155_REG0_SUBADDR
 USBILIM More...
 
#define LTC4155_USBILIM_SIZE   5
 
#define LTC4155_USBILIM_OFFSET   0
 
#define LTC4155_USBILIM_MASK   0x1F
 
#define LTC4155_USBILIM   (LTC4155_USBILIM_OFFSET << 12 | (LTC4155_USBILIM_SIZE - 1) << 8 | LTC4155_USBILIM_SUBADDR)
 
#define LTC4155_USBILIM_PRESET__100MA   0x0
 
#define LTC4155_USBILIM_PRESET__500MA   0x1
 
#define LTC4155_USBILIM_PRESET__600MA   0x2
 
#define LTC4155_USBILIM_PRESET__700MA   0x3
 
#define LTC4155_USBILIM_PRESET__800MA   0x4
 
#define LTC4155_USBILIM_PRESET__900MA   0x5
 
#define LTC4155_USBILIM_PRESET__1P00A   0x6
 
#define LTC4155_USBILIM_PRESET__1P25A   0x7
 
#define LTC4155_USBILIM_PRESET__1P50A   0x8
 
#define LTC4155_USBILIM_PRESET__1P75A   0x9
 
#define LTC4155_USBILIM_PRESET__2P00A   0xA
 
#define LTC4155_USBILIM_PRESET__2P25A   0xB
 
#define LTC4155_USBILIM_PRESET__2P50A   0xC
 
#define LTC4155_USBILIM_PRESET__2P75A   0xD
 
#define LTC4155_USBILIM_PRESET__3P00A   0xE
 
#define LTC4155_USBILIM_PRESET__2P5MA_SUSPEND   0xF
 
#define LTC4155_USBILIM_PRESET_CLPROG_1   0x1F
 
#define LTC4155_REG1_SUBADDR   0x01
 
#define LTC4155_REG1   (0 << 12 | (16 - 1) << 8 | LTC4155_REG1_SUBADDR)
 
#define LTC4155_PRIORITY_SUBADDR   LTC4155_REG1_SUBADDR
 PRIORITY More...
 
#define LTC4155_PRIORITY_SIZE   1
 
#define LTC4155_PRIORITY_OFFSET   7
 
#define LTC4155_PRIORITY_MASK   0x80
 
#define LTC4155_PRIORITY   (LTC4155_PRIORITY_OFFSET << 12 | (LTC4155_PRIORITY_SIZE - 1) << 8 | LTC4155_PRIORITY_SUBADDR)
 
#define LTC4155_PRIORITY_PRESET_WALL   0x0
 
#define LTC4155_PRIORITY_PRESET_USB   0x1
 
#define LTC4155_TIMER_SUBADDR   LTC4155_REG1_SUBADDR
 TIMER More...
 
#define LTC4155_TIMER_SIZE   2
 
#define LTC4155_TIMER_OFFSET   5
 
#define LTC4155_TIMER_MASK   0x60
 
#define LTC4155_TIMER   (LTC4155_TIMER_OFFSET << 12 | (LTC4155_TIMER_SIZE - 1) << 8 | LTC4155_TIMER_SUBADDR)
 
#define LTC4155_TIMER_PRESET__4_HOUR   0x0
 
#define LTC4155_TIMER_PRESET__8_HOUR_OR_COVERX   0x1
 
#define LTC4155_TIMER_PRESET__1_HOUR   0x2
 
#define LTC4155_TIMER_PRESET__2_HOUR   0x3
 
#define LTC4155_WALLILIM_SUBADDR   LTC4155_REG1_SUBADDR
 WALLILIM More...
 
#define LTC4155_WALLILIM_SIZE   5
 
#define LTC4155_WALLILIM_OFFSET   0
 
#define LTC4155_WALLILIM_MASK   0x1F
 
#define LTC4155_WALLILIM   (LTC4155_WALLILIM_OFFSET << 12 | (LTC4155_WALLILIM_SIZE - 1) << 8 | LTC4155_WALLILIM_SUBADDR)
 
#define LTC4155_WALLILIM_PRESET__100MA   0x0
 
#define LTC4155_WALLILIM_PRESET__500MA   0x1
 
#define LTC4155_WALLILIM_PRESET__600MA   0x2
 
#define LTC4155_WALLILIM_PRESET__700MA   0x3
 
#define LTC4155_WALLILIM_PRESET__800MA   0x4
 
#define LTC4155_WALLILIM_PRESET__900MA   0x5
 
#define LTC4155_WALLILIM_PRESET__1P00A   0x6
 
#define LTC4155_WALLILIM_PRESET__1P25A   0x7
 
#define LTC4155_WALLILIM_PRESET__1P50A   0x8
 
#define LTC4155_WALLILIM_PRESET__1P75A   0x9
 
#define LTC4155_WALLILIM_PRESET__2P00A   0xA
 
#define LTC4155_WALLILIM_PRESET__2P25A   0xB
 
#define LTC4155_WALLILIM_PRESET__2P50A   0xC
 
#define LTC4155_WALLILIM_PRESET__2P75A   0xD
 
#define LTC4155_WALLILIM_PRESET__3P00A   0xE
 
#define LTC4155_WALLILIM_PRESET__2P5MA_SUSPEND   0xF
 
#define LTC4155_WALLILIM_PRESET_CLPROG_1   0x1F
 
#define LTC4155_REG2_SUBADDR   0x02
 
#define LTC4155_REG2   (0 << 12 | (16 - 1) << 8 | LTC4155_REG2_SUBADDR)
 
#define LTC4155_ICHARGE_SUBADDR   LTC4155_REG2_SUBADDR
 ICHARGE More...
 
#define LTC4155_ICHARGE_SIZE   4
 
#define LTC4155_ICHARGE_OFFSET   4
 
#define LTC4155_ICHARGE_MASK   0xF0
 
#define LTC4155_ICHARGE   (LTC4155_ICHARGE_OFFSET << 12 | (LTC4155_ICHARGE_SIZE - 1) << 8 | LTC4155_ICHARGE_SUBADDR)
 
#define LTC4155_ICHARGE_PRESET_CHARGER_DISABLED   0x0
 
#define LTC4155_ICHARGE_PRESET__12P50PCT   0x1
 
#define LTC4155_ICHARGE_PRESET__18P75PCT   0x2
 
#define LTC4155_ICHARGE_PRESET__25P00PCT   0x3
 
#define LTC4155_ICHARGE_PRESET__31P25PCT   0x4
 
#define LTC4155_ICHARGE_PRESET__37P50PCT   0x5
 
#define LTC4155_ICHARGE_PRESET__43P75PCT   0x6
 
#define LTC4155_ICHARGE_PRESET__50P00PCT   0x7
 
#define LTC4155_ICHARGE_PRESET__56P25PCT   0x8
 
#define LTC4155_ICHARGE_PRESET__62P50PCT   0x9
 
#define LTC4155_ICHARGE_PRESET__68P75PCT   0xA
 
#define LTC4155_ICHARGE_PRESET__75P00PCT   0xB
 
#define LTC4155_ICHARGE_PRESET__81P25PCT   0xC
 
#define LTC4155_ICHARGE_PRESET__87P50PCT   0xD
 
#define LTC4155_ICHARGE_PRESET__93P75PCT   0xE
 
#define LTC4155_ICHARGE_PRESET__100P0PCT   0xF
 
#define LTC4155_VFLOAT_SUBADDR   LTC4155_REG2_SUBADDR
 VFLOAT More...
 
#define LTC4155_VFLOAT_SIZE   2
 
#define LTC4155_VFLOAT_OFFSET   2
 
#define LTC4155_VFLOAT_MASK   0x0C
 
#define LTC4155_VFLOAT   (LTC4155_VFLOAT_OFFSET << 12 | (LTC4155_VFLOAT_SIZE - 1) << 8 | LTC4155_VFLOAT_SUBADDR)
 
#define LTC4155_VFLOAT_PRESET__4P05V   0x0
 
#define LTC4155_VFLOAT_PRESET__4P10V   0x1
 
#define LTC4155_VFLOAT_PRESET__4P15V   0x2
 
#define LTC4155_VFLOAT_PRESET__4P20V   0x3
 
#define LTC4155_CXSET_SUBADDR   LTC4155_REG2_SUBADDR
 CXSET More...
 
#define LTC4155_CXSET_SIZE   2
 
#define LTC4155_CXSET_OFFSET   0
 
#define LTC4155_CXSET_MASK   0x03
 
#define LTC4155_CXSET   (LTC4155_CXSET_OFFSET << 12 | (LTC4155_CXSET_SIZE - 1) << 8 | LTC4155_CXSET_SUBADDR)
 
#define LTC4155_CXSET_PRESET__10PCT   0x0
 
#define LTC4155_CXSET_PRESET__20PCT   0x1
 
#define LTC4155_CXSET_PRESET__2PCT   0x2
 
#define LTC4155_CXSET_PRESET__5PCT   0x3
 
#define LTC4155_REG3_SUBADDR   0x03
 
#define LTC4155_REG3   (0 << 12 | (16 - 1) << 8 | LTC4155_REG3_SUBADDR)
 
#define LTC4155_CHARGER_STATUS_SUBADDR   LTC4155_REG3_SUBADDR
 CHARGER_STATUS More...
 
#define LTC4155_CHARGER_STATUS_SIZE   3
 
#define LTC4155_CHARGER_STATUS_OFFSET   5
 
#define LTC4155_CHARGER_STATUS_MASK   0xE0
 
#define LTC4155_CHARGER_STATUS   (LTC4155_CHARGER_STATUS_OFFSET << 12 | (LTC4155_CHARGER_STATUS_SIZE - 1) << 8 | LTC4155_CHARGER_STATUS_SUBADDR)
 
#define LTC4155_CHARGER_STATUS_PRESET_CHARGER_OFF   0x0
 
#define LTC4155_CHARGER_STATUS_PRESET_LOW_BAT   0x1
 
#define LTC4155_CHARGER_STATUS_PRESET_CONSTANT_CURRENT   0x2
 
#define LTC4155_CHARGER_STATUS_PRESET_CONSTANT_VOLTAGE_I_GREATER_THAN_COVERX   0x3
 
#define LTC4155_CHARGER_STATUS_PRESET_CONSTANT_VOLTAGE_I_LESS_THAN_COVERX   0x4
 
#define LTC4155_CHARGER_STATUS_PRESET_NTC_TOO_WARM_TO_CHARGE   0x5
 
#define LTC4155_CHARGER_STATUS_PRESET_NTC_TOO_COLD_TO_CHARGE   0x6
 
#define LTC4155_CHARGER_STATUS_PRESET_NTC_CRITICALLY_HOT   0x7
 
#define LTC4155_ID_PIN_DETECT_SUBADDR   LTC4155_REG3_SUBADDR
 ID_PIN_DETECT More...
 
#define LTC4155_ID_PIN_DETECT_SIZE   1
 
#define LTC4155_ID_PIN_DETECT_OFFSET   4
 
#define LTC4155_ID_PIN_DETECT_MASK   0x10
 
#define LTC4155_ID_PIN_DETECT   (LTC4155_ID_PIN_DETECT_OFFSET << 12 | (LTC4155_ID_PIN_DETECT_SIZE - 1) << 8 | LTC4155_ID_PIN_DETECT_SUBADDR)
 
#define LTC4155_OTG_ENABLED_SUBADDR   LTC4155_REG3_SUBADDR
 OTG_ENABLED More...
 
#define LTC4155_OTG_ENABLED_SIZE   1
 
#define LTC4155_OTG_ENABLED_OFFSET   3
 
#define LTC4155_OTG_ENABLED_MASK   0x08
 
#define LTC4155_OTG_ENABLED   (LTC4155_OTG_ENABLED_OFFSET << 12 | (LTC4155_OTG_ENABLED_SIZE - 1) << 8 | LTC4155_OTG_ENABLED_SUBADDR)
 
#define LTC4155_NTCSTAT_SUBADDR   LTC4155_REG3_SUBADDR
 NTCSTAT More...
 
#define LTC4155_NTCSTAT_SIZE   2
 
#define LTC4155_NTCSTAT_OFFSET   1
 
#define LTC4155_NTCSTAT_MASK   0x06
 
#define LTC4155_NTCSTAT   (LTC4155_NTCSTAT_OFFSET << 12 | (LTC4155_NTCSTAT_SIZE - 1) << 8 | LTC4155_NTCSTAT_SUBADDR)
 
#define LTC4155_NTCSTAT_PRESET_NORMAL   0x0
 
#define LTC4155_NTCSTAT_PRESET_TOO_COLD   0x1
 
#define LTC4155_NTCSTAT_PRESET_TOO_WARM   0x2
 
#define LTC4155_NTCSTAT_PRESET_HOT_FAULT   0x3
 
#define LTC4155_LOWBAT_SUBADDR   LTC4155_REG3_SUBADDR
 LOWBAT More...
 
#define LTC4155_LOWBAT_SIZE   1
 
#define LTC4155_LOWBAT_OFFSET   0
 
#define LTC4155_LOWBAT_MASK   0x01
 
#define LTC4155_LOWBAT   (LTC4155_LOWBAT_OFFSET << 12 | (LTC4155_LOWBAT_SIZE - 1) << 8 | LTC4155_LOWBAT_SUBADDR)
 
#define LTC4155_REG4_SUBADDR   0x04
 
#define LTC4155_REG4   (0 << 12 | (16 - 1) << 8 | LTC4155_REG4_SUBADDR)
 
#define LTC4155_EXT_PWR_GOOD_SUBADDR   LTC4155_REG4_SUBADDR
 EXT_PWR_GOOD More...
 
#define LTC4155_EXT_PWR_GOOD_SIZE   1
 
#define LTC4155_EXT_PWR_GOOD_OFFSET   7
 
#define LTC4155_EXT_PWR_GOOD_MASK   0x80
 
#define LTC4155_EXT_PWR_GOOD   (LTC4155_EXT_PWR_GOOD_OFFSET << 12 | (LTC4155_EXT_PWR_GOOD_SIZE - 1) << 8 | LTC4155_EXT_PWR_GOOD_SUBADDR)
 
#define LTC4155_USBSNS_GOOD_SUBADDR   LTC4155_REG4_SUBADDR
 USBSNS_GOOD More...
 
#define LTC4155_USBSNS_GOOD_SIZE   1
 
#define LTC4155_USBSNS_GOOD_OFFSET   6
 
#define LTC4155_USBSNS_GOOD_MASK   0x40
 
#define LTC4155_USBSNS_GOOD   (LTC4155_USBSNS_GOOD_OFFSET << 12 | (LTC4155_USBSNS_GOOD_SIZE - 1) << 8 | LTC4155_USBSNS_GOOD_SUBADDR)
 
#define LTC4155_WALLSNS_GOOD_SUBADDR   LTC4155_REG4_SUBADDR
 WALLSNS_GOOD More...
 
#define LTC4155_WALLSNS_GOOD_SIZE   1
 
#define LTC4155_WALLSNS_GOOD_OFFSET   5
 
#define LTC4155_WALLSNS_GOOD_MASK   0x20
 
#define LTC4155_WALLSNS_GOOD   (LTC4155_WALLSNS_GOOD_OFFSET << 12 | (LTC4155_WALLSNS_GOOD_SIZE - 1) << 8 | LTC4155_WALLSNS_GOOD_SUBADDR)
 
#define LTC4155_AT_INPUT_ILIM_SUBADDR   LTC4155_REG4_SUBADDR
 AT_INPUT_ILIM More...
 
#define LTC4155_AT_INPUT_ILIM_SIZE   1
 
#define LTC4155_AT_INPUT_ILIM_OFFSET   4
 
#define LTC4155_AT_INPUT_ILIM_MASK   0x10
 
#define LTC4155_AT_INPUT_ILIM   (LTC4155_AT_INPUT_ILIM_OFFSET << 12 | (LTC4155_AT_INPUT_ILIM_SIZE - 1) << 8 | LTC4155_AT_INPUT_ILIM_SUBADDR)
 
#define LTC4155_INPUT_UVCL_ACTIVE_SUBADDR   LTC4155_REG4_SUBADDR
 INPUT_UVCL_ACTIVE More...
 
#define LTC4155_INPUT_UVCL_ACTIVE_SIZE   1
 
#define LTC4155_INPUT_UVCL_ACTIVE_OFFSET   3
 
#define LTC4155_INPUT_UVCL_ACTIVE_MASK   0x08
 
#define LTC4155_INPUT_UVCL_ACTIVE   (LTC4155_INPUT_UVCL_ACTIVE_OFFSET << 12 | (LTC4155_INPUT_UVCL_ACTIVE_SIZE - 1) << 8 | LTC4155_INPUT_UVCL_ACTIVE_SUBADDR)
 
#define LTC4155_OVP_ACTIVE_SUBADDR   LTC4155_REG4_SUBADDR
 OVP_ACTIVE More...
 
#define LTC4155_OVP_ACTIVE_SIZE   1
 
#define LTC4155_OVP_ACTIVE_OFFSET   2
 
#define LTC4155_OVP_ACTIVE_MASK   0x04
 
#define LTC4155_OVP_ACTIVE   (LTC4155_OVP_ACTIVE_OFFSET << 12 | (LTC4155_OVP_ACTIVE_SIZE - 1) << 8 | LTC4155_OVP_ACTIVE_SUBADDR)
 
#define LTC4155_OTG_FAULT_SUBADDR   LTC4155_REG4_SUBADDR
 OTG_FAULT More...
 
#define LTC4155_OTG_FAULT_SIZE   1
 
#define LTC4155_OTG_FAULT_OFFSET   1
 
#define LTC4155_OTG_FAULT_MASK   0x02
 
#define LTC4155_OTG_FAULT   (LTC4155_OTG_FAULT_OFFSET << 12 | (LTC4155_OTG_FAULT_SIZE - 1) << 8 | LTC4155_OTG_FAULT_SUBADDR)
 
#define LTC4155_BAD_CELL_SUBADDR   LTC4155_REG4_SUBADDR
 BAD_CELL More...
 
#define LTC4155_BAD_CELL_SIZE   1
 
#define LTC4155_BAD_CELL_OFFSET   0
 
#define LTC4155_BAD_CELL_MASK   0x01
 
#define LTC4155_BAD_CELL   (LTC4155_BAD_CELL_OFFSET << 12 | (LTC4155_BAD_CELL_SIZE - 1) << 8 | LTC4155_BAD_CELL_SUBADDR)
 
#define LTC4155_REG5_SUBADDR   0x05
 
#define LTC4155_REG5   (0 << 12 | (16 - 1) << 8 | LTC4155_REG5_SUBADDR)
 
#define LTC4155_NTCVAL_SUBADDR   LTC4155_REG5_SUBADDR
 NTCVAL More...
 
#define LTC4155_NTCVAL_SIZE   7
 
#define LTC4155_NTCVAL_OFFSET   1
 
#define LTC4155_NTCVAL_MASK   0xFE
 
#define LTC4155_NTCVAL   (LTC4155_NTCVAL_OFFSET << 12 | (LTC4155_NTCVAL_SIZE - 1) << 8 | LTC4155_NTCVAL_SUBADDR)
 
#define LTC4155_NTC_WARNING_SUBADDR   LTC4155_REG5_SUBADDR
 NTC_WARNING More...
 
#define LTC4155_NTC_WARNING_SIZE   1
 
#define LTC4155_NTC_WARNING_OFFSET   0
 
#define LTC4155_NTC_WARNING_MASK   0x01
 
#define LTC4155_NTC_WARNING   (LTC4155_NTC_WARNING_OFFSET << 12 | (LTC4155_NTC_WARNING_SIZE - 1) << 8 | LTC4155_NTC_WARNING_SUBADDR)
 
#define LTC4155_REG6_SUBADDR   0x06
 
#define LTC4155_REG6   (0 << 12 | (16 - 1) << 8 | LTC4155_REG6_SUBADDR)
 
#define LTC4155_ENABLE_CHARGER_INT_SUBADDR   LTC4155_REG6_SUBADDR
 ENABLE_CHARGER_INT More...
 
#define LTC4155_ENABLE_CHARGER_INT_SIZE   1
 
#define LTC4155_ENABLE_CHARGER_INT_OFFSET   7
 
#define LTC4155_ENABLE_CHARGER_INT_MASK   0x80
 
#define LTC4155_ENABLE_CHARGER_INT   (LTC4155_ENABLE_CHARGER_INT_OFFSET << 12 | (LTC4155_ENABLE_CHARGER_INT_SIZE - 1) << 8 | LTC4155_ENABLE_CHARGER_INT_SUBADDR)
 
#define LTC4155_ENABLE_FAULT_INT_SUBADDR   LTC4155_REG6_SUBADDR
 ENABLE_FAULT_INT More...
 
#define LTC4155_ENABLE_FAULT_INT_SIZE   1
 
#define LTC4155_ENABLE_FAULT_INT_OFFSET   6
 
#define LTC4155_ENABLE_FAULT_INT_MASK   0x40
 
#define LTC4155_ENABLE_FAULT_INT   (LTC4155_ENABLE_FAULT_INT_OFFSET << 12 | (LTC4155_ENABLE_FAULT_INT_SIZE - 1) << 8 | LTC4155_ENABLE_FAULT_INT_SUBADDR)
 
#define LTC4155_ENABLE_EXTPWR_INT_SUBADDR   LTC4155_REG6_SUBADDR
 ENABLE_EXTPWR_INT More...
 
#define LTC4155_ENABLE_EXTPWR_INT_SIZE   1
 
#define LTC4155_ENABLE_EXTPWR_INT_OFFSET   5
 
#define LTC4155_ENABLE_EXTPWR_INT_MASK   0x20
 
#define LTC4155_ENABLE_EXTPWR_INT   (LTC4155_ENABLE_EXTPWR_INT_OFFSET << 12 | (LTC4155_ENABLE_EXTPWR_INT_SIZE - 1) << 8 | LTC4155_ENABLE_EXTPWR_INT_SUBADDR)
 
#define LTC4155_ENABLE_OTG_INT_SUBADDR   LTC4155_REG6_SUBADDR
 ENABLE_OTG_INT More...
 
#define LTC4155_ENABLE_OTG_INT_SIZE   1
 
#define LTC4155_ENABLE_OTG_INT_OFFSET   4
 
#define LTC4155_ENABLE_OTG_INT_MASK   0x10
 
#define LTC4155_ENABLE_OTG_INT   (LTC4155_ENABLE_OTG_INT_OFFSET << 12 | (LTC4155_ENABLE_OTG_INT_SIZE - 1) << 8 | LTC4155_ENABLE_OTG_INT_SUBADDR)
 
#define LTC4155_ENABLE_AT_ILIM_INT_SUBADDR   LTC4155_REG6_SUBADDR
 ENABLE_AT_ILIM_INT More...
 
#define LTC4155_ENABLE_AT_ILIM_INT_SIZE   1
 
#define LTC4155_ENABLE_AT_ILIM_INT_OFFSET   3
 
#define LTC4155_ENABLE_AT_ILIM_INT_MASK   0x08
 
#define LTC4155_ENABLE_AT_ILIM_INT   (LTC4155_ENABLE_AT_ILIM_INT_OFFSET << 12 | (LTC4155_ENABLE_AT_ILIM_INT_SIZE - 1) << 8 | LTC4155_ENABLE_AT_ILIM_INT_SUBADDR)
 
#define LTC4155_ENABLE_INPUT_UVCL_INT_SUBADDR   LTC4155_REG6_SUBADDR
 ENABLE_INPUT_UVCL_INT More...
 
#define LTC4155_ENABLE_INPUT_UVCL_INT_SIZE   1
 
#define LTC4155_ENABLE_INPUT_UVCL_INT_OFFSET   2
 
#define LTC4155_ENABLE_INPUT_UVCL_INT_MASK   0x04
 
#define LTC4155_ENABLE_INPUT_UVCL_INT   (LTC4155_ENABLE_INPUT_UVCL_INT_OFFSET << 12 | (LTC4155_ENABLE_INPUT_UVCL_INT_SIZE - 1) << 8 | LTC4155_ENABLE_INPUT_UVCL_INT_SUBADDR)
 
#define LTC4155_REQUEST_OTG_SUBADDR   LTC4155_REG6_SUBADDR
 REQUEST_OTG More...
 
#define LTC4155_REQUEST_OTG_SIZE   1
 
#define LTC4155_REQUEST_OTG_OFFSET   1
 
#define LTC4155_REQUEST_OTG_MASK   0x02
 
#define LTC4155_REQUEST_OTG   (LTC4155_REQUEST_OTG_OFFSET << 12 | (LTC4155_REQUEST_OTG_SIZE - 1) << 8 | LTC4155_REQUEST_OTG_SUBADDR)
 
#define LTC4155_RESERVED_SUBADDR   LTC4155_REG6_SUBADDR
 RESERVED More...
 
#define LTC4155_RESERVED_SIZE   1
 
#define LTC4155_RESERVED_OFFSET   0
 
#define LTC4155_RESERVED_MASK   0x01
 
#define LTC4155_RESERVED   (LTC4155_RESERVED_OFFSET << 12 | (LTC4155_RESERVED_SIZE - 1) << 8 | LTC4155_RESERVED_SUBADDR)
 
#define LTC4155_REG7_SUBADDR   0x07
 
#define LTC4155_REG7   (0 << 12 | (16 - 1) << 8 | LTC4155_REG7_SUBADDR)
 
#define LTC4155_ARM_SHIPMODE_SUBADDR   LTC4155_REG7_SUBADDR
 ARM_SHIPMODE More...
 
#define LTC4155_ARM_SHIPMODE_SIZE   8
 
#define LTC4155_ARM_SHIPMODE_OFFSET   0
 
#define LTC4155_ARM_SHIPMODE_MASK   0xFF
 
#define LTC4155_ARM_SHIPMODE   (LTC4155_ARM_SHIPMODE_OFFSET << 12 | (LTC4155_ARM_SHIPMODE_SIZE - 1) << 8 | LTC4155_ARM_SHIPMODE_SUBADDR)
 
#define LTC4155_ARM_SHIPMODE_PRESET_ARM   0x01
 

Macro Definition Documentation

◆ LTC4155_ADDR_09

#define LTC4155_ADDR_09   0x9

LTC4155 I2C address in 7-bit format.

Definition at line 77 of file LTC4155_reg_defs.h.