74 #ifndef LTC4155_REG_DEFS_H_ 75 #define LTC4155_REG_DEFS_H_ 77 #define LTC4155_ADDR_09 0x9 95 #define LTC4155_REG0_SUBADDR 0x00 96 #define LTC4155_REG0 (0 << 12 | (16 - 1) << 8 | LTC4155_REG0_SUBADDR) 113 #define LTC4155_DISABLE_INPUT_UVCL_SUBADDR LTC4155_REG0_SUBADDR 114 #define LTC4155_DISABLE_INPUT_UVCL_SIZE 1
115 #define LTC4155_DISABLE_INPUT_UVCL_OFFSET 7 116 #define LTC4155_DISABLE_INPUT_UVCL_MASK 0x80 117 #define LTC4155_DISABLE_INPUT_UVCL (LTC4155_DISABLE_INPUT_UVCL_OFFSET << 12 | (LTC4155_DISABLE_INPUT_UVCL_SIZE - 1) << 8 | LTC4155_DISABLE_INPUT_UVCL_SUBADDR) 134 #define LTC4155_EN_BAT_CONDITIONER_SUBADDR LTC4155_REG0_SUBADDR 135 #define LTC4155_EN_BAT_CONDITIONER_SIZE 1
136 #define LTC4155_EN_BAT_CONDITIONER_OFFSET 6 137 #define LTC4155_EN_BAT_CONDITIONER_MASK 0x40 138 #define LTC4155_EN_BAT_CONDITIONER (LTC4155_EN_BAT_CONDITIONER_OFFSET << 12 | (LTC4155_EN_BAT_CONDITIONER_SIZE - 1) << 8 | LTC4155_EN_BAT_CONDITIONER_SUBADDR) 155 #define LTC4155_LOCKOUT_ID_PIN_SUBADDR LTC4155_REG0_SUBADDR 156 #define LTC4155_LOCKOUT_ID_PIN_SIZE 1
157 #define LTC4155_LOCKOUT_ID_PIN_OFFSET 5 158 #define LTC4155_LOCKOUT_ID_PIN_MASK 0x20 159 #define LTC4155_LOCKOUT_ID_PIN (LTC4155_LOCKOUT_ID_PIN_OFFSET << 12 | (LTC4155_LOCKOUT_ID_PIN_SIZE - 1) << 8 | LTC4155_LOCKOUT_ID_PIN_SUBADDR) 176 #define LTC4155_USBILIM_SUBADDR LTC4155_REG0_SUBADDR 177 #define LTC4155_USBILIM_SIZE 5
178 #define LTC4155_USBILIM_OFFSET 0 179 #define LTC4155_USBILIM_MASK 0x1F 180 #define LTC4155_USBILIM (LTC4155_USBILIM_OFFSET << 12 | (LTC4155_USBILIM_SIZE - 1) << 8 | LTC4155_USBILIM_SUBADDR) 181 #define LTC4155_USBILIM_PRESET__100MA 0x0 182 #define LTC4155_USBILIM_PRESET__500MA 0x1 183 #define LTC4155_USBILIM_PRESET__600MA 0x2 184 #define LTC4155_USBILIM_PRESET__700MA 0x3 185 #define LTC4155_USBILIM_PRESET__800MA 0x4 186 #define LTC4155_USBILIM_PRESET__900MA 0x5 187 #define LTC4155_USBILIM_PRESET__1P00A 0x6 188 #define LTC4155_USBILIM_PRESET__1P25A 0x7 189 #define LTC4155_USBILIM_PRESET__1P50A 0x8 190 #define LTC4155_USBILIM_PRESET__1P75A 0x9 191 #define LTC4155_USBILIM_PRESET__2P00A 0xA 192 #define LTC4155_USBILIM_PRESET__2P25A 0xB 193 #define LTC4155_USBILIM_PRESET__2P50A 0xC 194 #define LTC4155_USBILIM_PRESET__2P75A 0xD 195 #define LTC4155_USBILIM_PRESET__3P00A 0xE 196 #define LTC4155_USBILIM_PRESET__2P5MA_SUSPEND 0xF 197 #define LTC4155_USBILIM_PRESET_CLPROG_1 0x1F 216 #define LTC4155_REG1_SUBADDR 0x01 217 #define LTC4155_REG1 (0 << 12 | (16 - 1) << 8 | LTC4155_REG1_SUBADDR) 234 #define LTC4155_PRIORITY_SUBADDR LTC4155_REG1_SUBADDR 235 #define LTC4155_PRIORITY_SIZE 1
236 #define LTC4155_PRIORITY_OFFSET 7 237 #define LTC4155_PRIORITY_MASK 0x80 238 #define LTC4155_PRIORITY (LTC4155_PRIORITY_OFFSET << 12 | (LTC4155_PRIORITY_SIZE - 1) << 8 | LTC4155_PRIORITY_SUBADDR) 239 #define LTC4155_PRIORITY_PRESET_WALL 0x0 240 #define LTC4155_PRIORITY_PRESET_USB 0x1 257 #define LTC4155_TIMER_SUBADDR LTC4155_REG1_SUBADDR 258 #define LTC4155_TIMER_SIZE 2
259 #define LTC4155_TIMER_OFFSET 5 260 #define LTC4155_TIMER_MASK 0x60 261 #define LTC4155_TIMER (LTC4155_TIMER_OFFSET << 12 | (LTC4155_TIMER_SIZE - 1) << 8 | LTC4155_TIMER_SUBADDR) 262 #define LTC4155_TIMER_PRESET__4_HOUR 0x0 263 #define LTC4155_TIMER_PRESET__8_HOUR_OR_COVERX 0x1 264 #define LTC4155_TIMER_PRESET__1_HOUR 0x2 265 #define LTC4155_TIMER_PRESET__2_HOUR 0x3 282 #define LTC4155_WALLILIM_SUBADDR LTC4155_REG1_SUBADDR 283 #define LTC4155_WALLILIM_SIZE 5
284 #define LTC4155_WALLILIM_OFFSET 0 285 #define LTC4155_WALLILIM_MASK 0x1F 286 #define LTC4155_WALLILIM (LTC4155_WALLILIM_OFFSET << 12 | (LTC4155_WALLILIM_SIZE - 1) << 8 | LTC4155_WALLILIM_SUBADDR) 287 #define LTC4155_WALLILIM_PRESET__100MA 0x0 288 #define LTC4155_WALLILIM_PRESET__500MA 0x1 289 #define LTC4155_WALLILIM_PRESET__600MA 0x2 290 #define LTC4155_WALLILIM_PRESET__700MA 0x3 291 #define LTC4155_WALLILIM_PRESET__800MA 0x4 292 #define LTC4155_WALLILIM_PRESET__900MA 0x5 293 #define LTC4155_WALLILIM_PRESET__1P00A 0x6 294 #define LTC4155_WALLILIM_PRESET__1P25A 0x7 295 #define LTC4155_WALLILIM_PRESET__1P50A 0x8 296 #define LTC4155_WALLILIM_PRESET__1P75A 0x9 297 #define LTC4155_WALLILIM_PRESET__2P00A 0xA 298 #define LTC4155_WALLILIM_PRESET__2P25A 0xB 299 #define LTC4155_WALLILIM_PRESET__2P50A 0xC 300 #define LTC4155_WALLILIM_PRESET__2P75A 0xD 301 #define LTC4155_WALLILIM_PRESET__3P00A 0xE 302 #define LTC4155_WALLILIM_PRESET__2P5MA_SUSPEND 0xF 303 #define LTC4155_WALLILIM_PRESET_CLPROG_1 0x1F 322 #define LTC4155_REG2_SUBADDR 0x02 323 #define LTC4155_REG2 (0 << 12 | (16 - 1) << 8 | LTC4155_REG2_SUBADDR) 340 #define LTC4155_ICHARGE_SUBADDR LTC4155_REG2_SUBADDR 341 #define LTC4155_ICHARGE_SIZE 4
342 #define LTC4155_ICHARGE_OFFSET 4 343 #define LTC4155_ICHARGE_MASK 0xF0 344 #define LTC4155_ICHARGE (LTC4155_ICHARGE_OFFSET << 12 | (LTC4155_ICHARGE_SIZE - 1) << 8 | LTC4155_ICHARGE_SUBADDR) 345 #define LTC4155_ICHARGE_PRESET_CHARGER_DISABLED 0x0 346 #define LTC4155_ICHARGE_PRESET__12P50PCT 0x1 347 #define LTC4155_ICHARGE_PRESET__18P75PCT 0x2 348 #define LTC4155_ICHARGE_PRESET__25P00PCT 0x3 349 #define LTC4155_ICHARGE_PRESET__31P25PCT 0x4 350 #define LTC4155_ICHARGE_PRESET__37P50PCT 0x5 351 #define LTC4155_ICHARGE_PRESET__43P75PCT 0x6 352 #define LTC4155_ICHARGE_PRESET__50P00PCT 0x7 353 #define LTC4155_ICHARGE_PRESET__56P25PCT 0x8 354 #define LTC4155_ICHARGE_PRESET__62P50PCT 0x9 355 #define LTC4155_ICHARGE_PRESET__68P75PCT 0xA 356 #define LTC4155_ICHARGE_PRESET__75P00PCT 0xB 357 #define LTC4155_ICHARGE_PRESET__81P25PCT 0xC 358 #define LTC4155_ICHARGE_PRESET__87P50PCT 0xD 359 #define LTC4155_ICHARGE_PRESET__93P75PCT 0xE 360 #define LTC4155_ICHARGE_PRESET__100P0PCT 0xF 377 #define LTC4155_VFLOAT_SUBADDR LTC4155_REG2_SUBADDR 378 #define LTC4155_VFLOAT_SIZE 2
379 #define LTC4155_VFLOAT_OFFSET 2 380 #define LTC4155_VFLOAT_MASK 0x0C 381 #define LTC4155_VFLOAT (LTC4155_VFLOAT_OFFSET << 12 | (LTC4155_VFLOAT_SIZE - 1) << 8 | LTC4155_VFLOAT_SUBADDR) 382 #define LTC4155_VFLOAT_PRESET__4P05V 0x0 383 #define LTC4155_VFLOAT_PRESET__4P10V 0x1 384 #define LTC4155_VFLOAT_PRESET__4P15V 0x2 385 #define LTC4155_VFLOAT_PRESET__4P20V 0x3 402 #define LTC4155_CXSET_SUBADDR LTC4155_REG2_SUBADDR 403 #define LTC4155_CXSET_SIZE 2
404 #define LTC4155_CXSET_OFFSET 0 405 #define LTC4155_CXSET_MASK 0x03 406 #define LTC4155_CXSET (LTC4155_CXSET_OFFSET << 12 | (LTC4155_CXSET_SIZE - 1) << 8 | LTC4155_CXSET_SUBADDR) 407 #define LTC4155_CXSET_PRESET__10PCT 0x0 408 #define LTC4155_CXSET_PRESET__20PCT 0x1 409 #define LTC4155_CXSET_PRESET__2PCT 0x2 410 #define LTC4155_CXSET_PRESET__5PCT 0x3 431 #define LTC4155_REG3_SUBADDR 0x03 432 #define LTC4155_REG3 (0 << 12 | (16 - 1) << 8 | LTC4155_REG3_SUBADDR) 449 #define LTC4155_CHARGER_STATUS_SUBADDR LTC4155_REG3_SUBADDR 450 #define LTC4155_CHARGER_STATUS_SIZE 3
451 #define LTC4155_CHARGER_STATUS_OFFSET 5 452 #define LTC4155_CHARGER_STATUS_MASK 0xE0 453 #define LTC4155_CHARGER_STATUS (LTC4155_CHARGER_STATUS_OFFSET << 12 | (LTC4155_CHARGER_STATUS_SIZE - 1) << 8 | LTC4155_CHARGER_STATUS_SUBADDR) 454 #define LTC4155_CHARGER_STATUS_PRESET_CHARGER_OFF 0x0 455 #define LTC4155_CHARGER_STATUS_PRESET_LOW_BAT 0x1 456 #define LTC4155_CHARGER_STATUS_PRESET_CONSTANT_CURRENT 0x2 457 #define LTC4155_CHARGER_STATUS_PRESET_CONSTANT_VOLTAGE_I_GREATER_THAN_COVERX 0x3 458 #define LTC4155_CHARGER_STATUS_PRESET_CONSTANT_VOLTAGE_I_LESS_THAN_COVERX 0x4 459 #define LTC4155_CHARGER_STATUS_PRESET_NTC_TOO_WARM_TO_CHARGE 0x5 460 #define LTC4155_CHARGER_STATUS_PRESET_NTC_TOO_COLD_TO_CHARGE 0x6 461 #define LTC4155_CHARGER_STATUS_PRESET_NTC_CRITICALLY_HOT 0x7 478 #define LTC4155_ID_PIN_DETECT_SUBADDR LTC4155_REG3_SUBADDR 479 #define LTC4155_ID_PIN_DETECT_SIZE 1
480 #define LTC4155_ID_PIN_DETECT_OFFSET 4 481 #define LTC4155_ID_PIN_DETECT_MASK 0x10 482 #define LTC4155_ID_PIN_DETECT (LTC4155_ID_PIN_DETECT_OFFSET << 12 | (LTC4155_ID_PIN_DETECT_SIZE - 1) << 8 | LTC4155_ID_PIN_DETECT_SUBADDR) 499 #define LTC4155_OTG_ENABLED_SUBADDR LTC4155_REG3_SUBADDR 500 #define LTC4155_OTG_ENABLED_SIZE 1
501 #define LTC4155_OTG_ENABLED_OFFSET 3 502 #define LTC4155_OTG_ENABLED_MASK 0x08 503 #define LTC4155_OTG_ENABLED (LTC4155_OTG_ENABLED_OFFSET << 12 | (LTC4155_OTG_ENABLED_SIZE - 1) << 8 | LTC4155_OTG_ENABLED_SUBADDR) 520 #define LTC4155_NTCSTAT_SUBADDR LTC4155_REG3_SUBADDR 521 #define LTC4155_NTCSTAT_SIZE 2
522 #define LTC4155_NTCSTAT_OFFSET 1 523 #define LTC4155_NTCSTAT_MASK 0x06 524 #define LTC4155_NTCSTAT (LTC4155_NTCSTAT_OFFSET << 12 | (LTC4155_NTCSTAT_SIZE - 1) << 8 | LTC4155_NTCSTAT_SUBADDR) 525 #define LTC4155_NTCSTAT_PRESET_NORMAL 0x0 526 #define LTC4155_NTCSTAT_PRESET_TOO_COLD 0x1 527 #define LTC4155_NTCSTAT_PRESET_TOO_WARM 0x2 528 #define LTC4155_NTCSTAT_PRESET_HOT_FAULT 0x3 545 #define LTC4155_LOWBAT_SUBADDR LTC4155_REG3_SUBADDR 546 #define LTC4155_LOWBAT_SIZE 1
547 #define LTC4155_LOWBAT_OFFSET 0 548 #define LTC4155_LOWBAT_MASK 0x01 549 #define LTC4155_LOWBAT (LTC4155_LOWBAT_OFFSET << 12 | (LTC4155_LOWBAT_SIZE - 1) << 8 | LTC4155_LOWBAT_SUBADDR) 573 #define LTC4155_REG4_SUBADDR 0x04 574 #define LTC4155_REG4 (0 << 12 | (16 - 1) << 8 | LTC4155_REG4_SUBADDR) 591 #define LTC4155_EXT_PWR_GOOD_SUBADDR LTC4155_REG4_SUBADDR 592 #define LTC4155_EXT_PWR_GOOD_SIZE 1
593 #define LTC4155_EXT_PWR_GOOD_OFFSET 7 594 #define LTC4155_EXT_PWR_GOOD_MASK 0x80 595 #define LTC4155_EXT_PWR_GOOD (LTC4155_EXT_PWR_GOOD_OFFSET << 12 | (LTC4155_EXT_PWR_GOOD_SIZE - 1) << 8 | LTC4155_EXT_PWR_GOOD_SUBADDR) 612 #define LTC4155_USBSNS_GOOD_SUBADDR LTC4155_REG4_SUBADDR 613 #define LTC4155_USBSNS_GOOD_SIZE 1
614 #define LTC4155_USBSNS_GOOD_OFFSET 6 615 #define LTC4155_USBSNS_GOOD_MASK 0x40 616 #define LTC4155_USBSNS_GOOD (LTC4155_USBSNS_GOOD_OFFSET << 12 | (LTC4155_USBSNS_GOOD_SIZE - 1) << 8 | LTC4155_USBSNS_GOOD_SUBADDR) 633 #define LTC4155_WALLSNS_GOOD_SUBADDR LTC4155_REG4_SUBADDR 634 #define LTC4155_WALLSNS_GOOD_SIZE 1
635 #define LTC4155_WALLSNS_GOOD_OFFSET 5 636 #define LTC4155_WALLSNS_GOOD_MASK 0x20 637 #define LTC4155_WALLSNS_GOOD (LTC4155_WALLSNS_GOOD_OFFSET << 12 | (LTC4155_WALLSNS_GOOD_SIZE - 1) << 8 | LTC4155_WALLSNS_GOOD_SUBADDR) 654 #define LTC4155_AT_INPUT_ILIM_SUBADDR LTC4155_REG4_SUBADDR 655 #define LTC4155_AT_INPUT_ILIM_SIZE 1
656 #define LTC4155_AT_INPUT_ILIM_OFFSET 4 657 #define LTC4155_AT_INPUT_ILIM_MASK 0x10 658 #define LTC4155_AT_INPUT_ILIM (LTC4155_AT_INPUT_ILIM_OFFSET << 12 | (LTC4155_AT_INPUT_ILIM_SIZE - 1) << 8 | LTC4155_AT_INPUT_ILIM_SUBADDR) 675 #define LTC4155_INPUT_UVCL_ACTIVE_SUBADDR LTC4155_REG4_SUBADDR 676 #define LTC4155_INPUT_UVCL_ACTIVE_SIZE 1
677 #define LTC4155_INPUT_UVCL_ACTIVE_OFFSET 3 678 #define LTC4155_INPUT_UVCL_ACTIVE_MASK 0x08 679 #define LTC4155_INPUT_UVCL_ACTIVE (LTC4155_INPUT_UVCL_ACTIVE_OFFSET << 12 | (LTC4155_INPUT_UVCL_ACTIVE_SIZE - 1) << 8 | LTC4155_INPUT_UVCL_ACTIVE_SUBADDR) 696 #define LTC4155_OVP_ACTIVE_SUBADDR LTC4155_REG4_SUBADDR 697 #define LTC4155_OVP_ACTIVE_SIZE 1
698 #define LTC4155_OVP_ACTIVE_OFFSET 2 699 #define LTC4155_OVP_ACTIVE_MASK 0x04 700 #define LTC4155_OVP_ACTIVE (LTC4155_OVP_ACTIVE_OFFSET << 12 | (LTC4155_OVP_ACTIVE_SIZE - 1) << 8 | LTC4155_OVP_ACTIVE_SUBADDR) 717 #define LTC4155_OTG_FAULT_SUBADDR LTC4155_REG4_SUBADDR 718 #define LTC4155_OTG_FAULT_SIZE 1
719 #define LTC4155_OTG_FAULT_OFFSET 1 720 #define LTC4155_OTG_FAULT_MASK 0x02 721 #define LTC4155_OTG_FAULT (LTC4155_OTG_FAULT_OFFSET << 12 | (LTC4155_OTG_FAULT_SIZE - 1) << 8 | LTC4155_OTG_FAULT_SUBADDR) 738 #define LTC4155_BAD_CELL_SUBADDR LTC4155_REG4_SUBADDR 739 #define LTC4155_BAD_CELL_SIZE 1
740 #define LTC4155_BAD_CELL_OFFSET 0 741 #define LTC4155_BAD_CELL_MASK 0x01 742 #define LTC4155_BAD_CELL (LTC4155_BAD_CELL_OFFSET << 12 | (LTC4155_BAD_CELL_SIZE - 1) << 8 | LTC4155_BAD_CELL_SUBADDR) 760 #define LTC4155_REG5_SUBADDR 0x05 761 #define LTC4155_REG5 (0 << 12 | (16 - 1) << 8 | LTC4155_REG5_SUBADDR) 778 #define LTC4155_NTCVAL_SUBADDR LTC4155_REG5_SUBADDR 779 #define LTC4155_NTCVAL_SIZE 7
780 #define LTC4155_NTCVAL_OFFSET 1 781 #define LTC4155_NTCVAL_MASK 0xFE 782 #define LTC4155_NTCVAL (LTC4155_NTCVAL_OFFSET << 12 | (LTC4155_NTCVAL_SIZE - 1) << 8 | LTC4155_NTCVAL_SUBADDR) 799 #define LTC4155_NTC_WARNING_SUBADDR LTC4155_REG5_SUBADDR 800 #define LTC4155_NTC_WARNING_SIZE 1
801 #define LTC4155_NTC_WARNING_OFFSET 0 802 #define LTC4155_NTC_WARNING_MASK 0x01 803 #define LTC4155_NTC_WARNING (LTC4155_NTC_WARNING_OFFSET << 12 | (LTC4155_NTC_WARNING_SIZE - 1) << 8 | LTC4155_NTC_WARNING_SUBADDR) 828 #define LTC4155_REG6_SUBADDR 0x06 829 #define LTC4155_REG6 (0 << 12 | (16 - 1) << 8 | LTC4155_REG6_SUBADDR) 846 #define LTC4155_ENABLE_CHARGER_INT_SUBADDR LTC4155_REG6_SUBADDR 847 #define LTC4155_ENABLE_CHARGER_INT_SIZE 1
848 #define LTC4155_ENABLE_CHARGER_INT_OFFSET 7 849 #define LTC4155_ENABLE_CHARGER_INT_MASK 0x80 850 #define LTC4155_ENABLE_CHARGER_INT (LTC4155_ENABLE_CHARGER_INT_OFFSET << 12 | (LTC4155_ENABLE_CHARGER_INT_SIZE - 1) << 8 | LTC4155_ENABLE_CHARGER_INT_SUBADDR) 867 #define LTC4155_ENABLE_FAULT_INT_SUBADDR LTC4155_REG6_SUBADDR 868 #define LTC4155_ENABLE_FAULT_INT_SIZE 1
869 #define LTC4155_ENABLE_FAULT_INT_OFFSET 6 870 #define LTC4155_ENABLE_FAULT_INT_MASK 0x40 871 #define LTC4155_ENABLE_FAULT_INT (LTC4155_ENABLE_FAULT_INT_OFFSET << 12 | (LTC4155_ENABLE_FAULT_INT_SIZE - 1) << 8 | LTC4155_ENABLE_FAULT_INT_SUBADDR) 888 #define LTC4155_ENABLE_EXTPWR_INT_SUBADDR LTC4155_REG6_SUBADDR 889 #define LTC4155_ENABLE_EXTPWR_INT_SIZE 1
890 #define LTC4155_ENABLE_EXTPWR_INT_OFFSET 5 891 #define LTC4155_ENABLE_EXTPWR_INT_MASK 0x20 892 #define LTC4155_ENABLE_EXTPWR_INT (LTC4155_ENABLE_EXTPWR_INT_OFFSET << 12 | (LTC4155_ENABLE_EXTPWR_INT_SIZE - 1) << 8 | LTC4155_ENABLE_EXTPWR_INT_SUBADDR) 909 #define LTC4155_ENABLE_OTG_INT_SUBADDR LTC4155_REG6_SUBADDR 910 #define LTC4155_ENABLE_OTG_INT_SIZE 1
911 #define LTC4155_ENABLE_OTG_INT_OFFSET 4 912 #define LTC4155_ENABLE_OTG_INT_MASK 0x10 913 #define LTC4155_ENABLE_OTG_INT (LTC4155_ENABLE_OTG_INT_OFFSET << 12 | (LTC4155_ENABLE_OTG_INT_SIZE - 1) << 8 | LTC4155_ENABLE_OTG_INT_SUBADDR) 930 #define LTC4155_ENABLE_AT_ILIM_INT_SUBADDR LTC4155_REG6_SUBADDR 931 #define LTC4155_ENABLE_AT_ILIM_INT_SIZE 1
932 #define LTC4155_ENABLE_AT_ILIM_INT_OFFSET 3 933 #define LTC4155_ENABLE_AT_ILIM_INT_MASK 0x08 934 #define LTC4155_ENABLE_AT_ILIM_INT (LTC4155_ENABLE_AT_ILIM_INT_OFFSET << 12 | (LTC4155_ENABLE_AT_ILIM_INT_SIZE - 1) << 8 | LTC4155_ENABLE_AT_ILIM_INT_SUBADDR) 951 #define LTC4155_ENABLE_INPUT_UVCL_INT_SUBADDR LTC4155_REG6_SUBADDR 952 #define LTC4155_ENABLE_INPUT_UVCL_INT_SIZE 1
953 #define LTC4155_ENABLE_INPUT_UVCL_INT_OFFSET 2 954 #define LTC4155_ENABLE_INPUT_UVCL_INT_MASK 0x04 955 #define LTC4155_ENABLE_INPUT_UVCL_INT (LTC4155_ENABLE_INPUT_UVCL_INT_OFFSET << 12 | (LTC4155_ENABLE_INPUT_UVCL_INT_SIZE - 1) << 8 | LTC4155_ENABLE_INPUT_UVCL_INT_SUBADDR) 972 #define LTC4155_REQUEST_OTG_SUBADDR LTC4155_REG6_SUBADDR 973 #define LTC4155_REQUEST_OTG_SIZE 1
974 #define LTC4155_REQUEST_OTG_OFFSET 1 975 #define LTC4155_REQUEST_OTG_MASK 0x02 976 #define LTC4155_REQUEST_OTG (LTC4155_REQUEST_OTG_OFFSET << 12 | (LTC4155_REQUEST_OTG_SIZE - 1) << 8 | LTC4155_REQUEST_OTG_SUBADDR) 993 #define LTC4155_RESERVED_SUBADDR LTC4155_REG6_SUBADDR 994 #define LTC4155_RESERVED_SIZE 1
995 #define LTC4155_RESERVED_OFFSET 0 996 #define LTC4155_RESERVED_MASK 0x01 997 #define LTC4155_RESERVED (LTC4155_RESERVED_OFFSET << 12 | (LTC4155_RESERVED_SIZE - 1) << 8 | LTC4155_RESERVED_SUBADDR) 1014 #define LTC4155_REG7_SUBADDR 0x07 1015 #define LTC4155_REG7 (0 << 12 | (16 - 1) << 8 | LTC4155_REG7_SUBADDR) 1032 #define LTC4155_ARM_SHIPMODE_SUBADDR LTC4155_REG7_SUBADDR 1033 #define LTC4155_ARM_SHIPMODE_SIZE 8
1034 #define LTC4155_ARM_SHIPMODE_OFFSET 0 1035 #define LTC4155_ARM_SHIPMODE_MASK 0xFF 1036 #define LTC4155_ARM_SHIPMODE (LTC4155_ARM_SHIPMODE_OFFSET << 12 | (LTC4155_ARM_SHIPMODE_SIZE - 1) << 8 | LTC4155_ARM_SHIPMODE_SUBADDR) 1037 #define LTC4155_ARM_SHIPMODE_PRESET_ARM 0x01