ADC SoC Board Configuration

ADC SoC Board Configuration

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Copyright © 2003-2016 Terasic Inc. All Rights Reserved.

Pin Assignments:

CLOCK
Name Location Direction IO Standard
FPGA_CLK1_50 V11 input 3.3-V LVTTL
FPGA_CLK2_50 Y13 input 3.3-V LVTTL
FPGA_CLK3_50 E11 input 3.3-V LVTTL

KEY
Name Location Direction IO Standard
KEY[0] AH17 input 3.3-V LVTTL
KEY[1] AH16 input 3.3-V LVTTL

SW
Name Location Direction IO Standard
SW[0] Y11 input 3.3-V LVTTL
SW[1] AA11 input 3.3-V LVTTL
SW[2] AD5 input 3.3-V LVTTL
SW[3] AE6 input 3.3-V LVTTL

LED
Name Location Direction IO Standard
LED[0] W15 output 3.3-V LVTTL
LED[1] AA24 output 3.3-V LVTTL
LED[2] V16 output 3.3-V LVTTL
LED[3] V15 output 3.3-V LVTTL
LED[4] AF26 output 3.3-V LVTTL
LED[5] AE26 output 3.3-V LVTTL
LED[6] Y16 output 3.3-V LVTTL
LED[7] AA23 output 3.3-V LVTTL

HDMI
Name Location Direction IO Standard
HDMI_I2C_SCL U10 inout 3.3-V LVTTL
HDMI_I2C_SDA AA4 inout 3.3-V LVTTL

ADC
Name Location Direction IO Standard
ADC_SCK V10 output 3.3-V LVTTL
ADC_SDO AD4 input 3.3-V LVTTL
ADC_SDI AC4 output 3.3-V LVTTL
ADC_CONVST U9 output 3.3-V LVTTL

GPIO
Name Location Direction IO Standard
GPIO_1[0] Y15 inout 3.3-V LVTTL
GPIO_1[1] AC24 inout 3.3-V LVTTL
GPIO_1[2] AA15 inout 3.3-V LVTTL
GPIO_1[3] AD23 inout 3.3-V LVTTL
GPIO_1[4] AG28 inout 3.3-V LVTTL
GPIO_1[5] AF28 inout 3.3-V LVTTL
GPIO_1[6] AE25 inout 3.3-V LVTTL
GPIO_1[7] AF27 inout 3.3-V LVTTL
GPIO_1[8] AG26 inout 3.3-V LVTTL
GPIO_1[9] AH27 inout 3.3-V LVTTL
GPIO_1[10] AG25 inout 3.3-V LVTTL
GPIO_1[11] AH26 inout 3.3-V LVTTL
GPIO_1[12] AH24 inout 3.3-V LVTTL
GPIO_1[13] AF25 inout 3.3-V LVTTL
GPIO_1[14] AG23 inout 3.3-V LVTTL
GPIO_1[15] AF23 inout 3.3-V LVTTL
GPIO_1[16] AG24 inout 3.3-V LVTTL
GPIO_1[17] AH22 inout 3.3-V LVTTL
GPIO_1[18] AH21 inout 3.3-V LVTTL
GPIO_1[19] AG21 inout 3.3-V LVTTL
GPIO_1[20] AH23 inout 3.3-V LVTTL
GPIO_1[21] AA20 inout 3.3-V LVTTL
GPIO_1[22] AF22 inout 3.3-V LVTTL
GPIO_1[23] AE22 inout 3.3-V LVTTL
GPIO_1[24] AG20 inout 3.3-V LVTTL
GPIO_1[25] AF21 inout 3.3-V LVTTL
GPIO_1[26] AG19 inout 3.3-V LVTTL
GPIO_1[27] AH19 inout 3.3-V LVTTL
GPIO_1[28] AG18 inout 3.3-V LVTTL
GPIO_1[29] AH18 inout 3.3-V LVTTL
GPIO_1[30] AF18 inout 3.3-V LVTTL
GPIO_1[31] AF20 inout 3.3-V LVTTL
GPIO_1[32] AG15 inout 3.3-V LVTTL
GPIO_1[33] AE20 inout 3.3-V LVTTL
GPIO_1[34] AE19 inout 3.3-V LVTTL
GPIO_1[35] AE17 inout 3.3-V LVTTL

ARDUINO
Name Location Direction IO Standard
ARDUINO_IO[0] AG13 inout 3.3-V LVTTL
ARDUINO_IO[1] AF13 inout 3.3-V LVTTL
ARDUINO_IO[2] AG10 inout 3.3-V LVTTL
ARDUINO_IO[3] AG9 inout 3.3-V LVTTL
ARDUINO_IO[4] U14 inout 3.3-V LVTTL
ARDUINO_IO[5] U13 inout 3.3-V LVTTL
ARDUINO_IO[6] AG8 inout 3.3-V LVTTL
ARDUINO_IO[7] AH8 inout 3.3-V LVTTL
ARDUINO_IO[8] AF17 inout 3.3-V LVTTL
ARDUINO_IO[9] AE15 inout 3.3-V LVTTL
ARDUINO_IO[10] AF15 inout 3.3-V LVTTL
ARDUINO_IO[11] AG16 inout 3.3-V LVTTL
ARDUINO_IO[12] AH11 inout 3.3-V LVTTL
ARDUINO_IO[13] AH12 inout 3.3-V LVTTL
ARDUINO_IO[14] AH9 inout 3.3-V LVTTL
ARDUINO_IO[15] AG11 inout 3.3-V LVTTL
ARDUINO_RESET_N AH7 inout 3.3-V LVTTL

DCC
Name Location Direction IO Standard
ADA_CLK_P AG5 output 3.3-V LVTTL
ADA_CLK_N AH4 output 3.3-V LVTTL
ADB_CLK_P E8 output 3.3-V LVTTL
ADB_CLK_N D8 output 3.3-V LVTTL
AD_SCLK T11 inout 3.3-V LVTTL
AD_SDIO U11 inout 3.3-V LVTTL
ADA_SPI_CS AA19 output 3.3-V LVTTL
ADB_SPI_CS AD19 output 3.3-V LVTTL
ADA_D[0] AC22 input 3.3-V LVTTL
ADA_D[1] AC23 input 3.3-V LVTTL
ADA_D[2] AD17 input 3.3-V LVTTL
ADA_D[3] AH3 input 3.3-V LVTTL
ADA_D[4] AF7 input 3.3-V LVTTL
ADA_D[5] AH13 input 3.3-V LVTTL
ADA_D[6] AF4 input 3.3-V LVTTL
ADA_D[7] AH14 input 3.3-V LVTTL
ADA_D[8] AE9 input 3.3-V LVTTL
ADA_D[9] AE7 input 3.3-V LVTTL
ADA_D[10] AE8 input 3.3-V LVTTL
ADA_D[11] AE4 input 3.3-V LVTTL
ADA_D[12] AE23 input 3.3-V LVTTL
ADA_D[13] AE24 input 3.3-V LVTTL
ADA_DCO V12 input 3.3-V LVTTL
ADA_OE Y17 output 3.3-V LVTTL
ADA_OR AG14 input 3.3-V LVTTL
ADA_PWDN Y18 output 3.3-V LVTTL
ADB_D[0] AH2 input 3.3-V LVTTL
ADB_D[1] AH5 input 3.3-V LVTTL
ADB_D[2] AF5 input 3.3-V LVTTL
ADB_D[3] AG6 input 3.3-V LVTTL
ADB_D[4] AF6 input 3.3-V LVTTL
ADB_D[5] AH6 input 3.3-V LVTTL
ADB_D[6] AF8 input 3.3-V LVTTL
ADB_D[7] AF9 input 3.3-V LVTTL
ADB_D[8] AF10 input 3.3-V LVTTL
ADB_D[9] AF11 input 3.3-V LVTTL
ADB_D[10] AD10 input 3.3-V LVTTL
ADB_D[11] AE11 input 3.3-V LVTTL
ADB_D[12] AD11 input 3.3-V LVTTL
ADB_D[13] AE12 input 3.3-V LVTTL
ADB_DCO D12 input 3.3-V LVTTL
ADB_OE T12 output 3.3-V LVTTL
ADB_OR AD12 input 3.3-V LVTTL
ADB_PWDN T13 output 3.3-V LVTTL

HPS
Name Location Direction IO Standard
HPS_CONV_USB_N C6 inout 3.3-V LVTTL
HPS_DDR3_ADDR[0] C28 output SSTL-15 Class I
HPS_DDR3_ADDR[1] B28 output SSTL-15 Class I
HPS_DDR3_ADDR[2] E26 output SSTL-15 Class I
HPS_DDR3_ADDR[3] D26 output SSTL-15 Class I
HPS_DDR3_ADDR[4] J21 output SSTL-15 Class I
HPS_DDR3_ADDR[5] J20 output SSTL-15 Class I
HPS_DDR3_ADDR[6] C26 output SSTL-15 Class I
HPS_DDR3_ADDR[7] B26 output SSTL-15 Class I
HPS_DDR3_ADDR[8] F26 output SSTL-15 Class I
HPS_DDR3_ADDR[9] F25 output SSTL-15 Class I
HPS_DDR3_ADDR[10] A24 output SSTL-15 Class I
HPS_DDR3_ADDR[11] B24 output SSTL-15 Class I
HPS_DDR3_ADDR[12] D24 output SSTL-15 Class I
HPS_DDR3_ADDR[13] C24 output SSTL-15 Class I
HPS_DDR3_ADDR[14] G23 output SSTL-15 Class I
HPS_DDR3_BA[0] A27 output SSTL-15 Class I
HPS_DDR3_BA[1] H25 output SSTL-15 Class I
HPS_DDR3_BA[2] G25 output SSTL-15 Class I
HPS_DDR3_CAS_N A26 output SSTL-15 Class I
HPS_DDR3_CKE L28 output SSTL-15 Class I
HPS_DDR3_CK_N N20 output Differential 1.5-V SSTL Class I
HPS_DDR3_CK_P N21 output Differential 1.5-V SSTL Class I
HPS_DDR3_CS_N L21 output SSTL-15 Class I
HPS_DDR3_DM[0] G28 output SSTL-15 Class I
HPS_DDR3_DM[1] P28 output SSTL-15 Class I
HPS_DDR3_DM[2] W28 output SSTL-15 Class I
HPS_DDR3_DM[3] AB28 output SSTL-15 Class I
HPS_DDR3_DQ[0] J25 inout SSTL-15 Class I
HPS_DDR3_DQ[1] J24 inout SSTL-15 Class I
HPS_DDR3_DQ[2] E28 inout SSTL-15 Class I
HPS_DDR3_DQ[3] D27 inout SSTL-15 Class I
HPS_DDR3_DQ[4] J26 inout SSTL-15 Class I
HPS_DDR3_DQ[5] K26 inout SSTL-15 Class I
HPS_DDR3_DQ[6] G27 inout SSTL-15 Class I
HPS_DDR3_DQ[7] F28 inout SSTL-15 Class I
HPS_DDR3_DQ[8] K25 inout SSTL-15 Class I
HPS_DDR3_DQ[9] L25 inout SSTL-15 Class I
HPS_DDR3_DQ[10] J27 inout SSTL-15 Class I
HPS_DDR3_DQ[11] J28 inout SSTL-15 Class I
HPS_DDR3_DQ[12] M27 inout SSTL-15 Class I
HPS_DDR3_DQ[13] M26 inout SSTL-15 Class I
HPS_DDR3_DQ[14] M28 inout SSTL-15 Class I
HPS_DDR3_DQ[15] N28 inout SSTL-15 Class I
HPS_DDR3_DQ[16] N24 inout SSTL-15 Class I
HPS_DDR3_DQ[17] N25 inout SSTL-15 Class I
HPS_DDR3_DQ[18] T28 inout SSTL-15 Class I
HPS_DDR3_DQ[19] U28 inout SSTL-15 Class I
HPS_DDR3_DQ[20] N26 inout SSTL-15 Class I
HPS_DDR3_DQ[21] N27 inout SSTL-15 Class I
HPS_DDR3_DQ[22] R27 inout SSTL-15 Class I
HPS_DDR3_DQ[23] V27 inout SSTL-15 Class I
HPS_DDR3_DQ[24] R26 inout SSTL-15 Class I
HPS_DDR3_DQ[25] R25 inout SSTL-15 Class I
HPS_DDR3_DQ[26] AA28 inout SSTL-15 Class I
HPS_DDR3_DQ[27] W26 inout SSTL-15 Class I
HPS_DDR3_DQ[28] R24 inout SSTL-15 Class I
HPS_DDR3_DQ[29] T24 inout SSTL-15 Class I
HPS_DDR3_DQ[30] Y27 inout SSTL-15 Class I
HPS_DDR3_DQ[31] AA27 inout SSTL-15 Class I
HPS_DDR3_DQS_N[0] R16 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N[1] R18 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N[2] T18 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N[3] T20 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[0] R17 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[1] R19 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[2] T19 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[3] U19 inout Differential 1.5-V SSTL Class I
HPS_DDR3_ODT D28 output SSTL-15 Class I
HPS_DDR3_RAS_N A25 output SSTL-15 Class I
HPS_DDR3_RESET_N V28 output SSTL-15 Class I
HPS_DDR3_RZQ D25 input 1.5 V
HPS_DDR3_WE_N E25 output SSTL-15 Class I
HPS_ENET_GTX_CLK J15 output 3.3-V LVTTL
HPS_ENET_INT_N B14 inout 3.3-V LVTTL
HPS_ENET_MDC A13 output 3.3-V LVTTL
HPS_ENET_MDIO E16 inout 3.3-V LVTTL
HPS_ENET_RX_CLK J12 input 3.3-V LVTTL
HPS_ENET_RX_DATA[0] A14 input 3.3-V LVTTL
HPS_ENET_RX_DATA[1] A11 input 3.3-V LVTTL
HPS_ENET_RX_DATA[2] C15 input 3.3-V LVTTL
HPS_ENET_RX_DATA[3] A9 input 3.3-V LVTTL
HPS_ENET_RX_DV J13 input 3.3-V LVTTL
HPS_ENET_TX_DATA[0] A16 output 3.3-V LVTTL
HPS_ENET_TX_DATA[1] J14 output 3.3-V LVTTL
HPS_ENET_TX_DATA[2] A15 output 3.3-V LVTTL
HPS_ENET_TX_DATA[3] D17 output 3.3-V LVTTL
HPS_ENET_TX_EN A12 output 3.3-V LVTTL
HPS_GSENSOR_INT A17 inout 3.3-V LVTTL
HPS_I2C0_SCLK C18 inout 3.3-V LVTTL
HPS_I2C0_SDAT A19 inout 3.3-V LVTTL
HPS_I2C1_SCLK K18 inout 3.3-V LVTTL
HPS_I2C1_SDAT A21 inout 3.3-V LVTTL
HPS_KEY J18 inout 3.3-V LVTTL
HPS_LED A20 inout 3.3-V LVTTL
HPS_LTC_GPIO H13 inout 3.3-V LVTTL
HPS_SD_CLK B8 output 3.3-V LVTTL
HPS_SD_CMD D14 inout 3.3-V LVTTL
HPS_SD_DATA[0] C13 inout 3.3-V LVTTL
HPS_SD_DATA[1] B6 inout 3.3-V LVTTL
HPS_SD_DATA[2] B11 inout 3.3-V LVTTL
HPS_SD_DATA[3] B9 inout 3.3-V LVTTL
HPS_SPIM_CLK C19 output 3.3-V LVTTL
HPS_SPIM_MISO B19 input 3.3-V LVTTL
HPS_SPIM_MOSI B16 output 3.3-V LVTTL
HPS_SPIM_SS C16 inout 3.3-V LVTTL
HPS_UART_RX A22 input 3.3-V LVTTL
HPS_UART_TX B21 output 3.3-V LVTTL
HPS_USB_CLKOUT G4 input 3.3-V LVTTL
HPS_USB_DATA[0] C10 inout 3.3-V LVTTL
HPS_USB_DATA[1] F5 inout 3.3-V LVTTL
HPS_USB_DATA[2] C9 inout 3.3-V LVTTL
HPS_USB_DATA[3] C4 inout 3.3-V LVTTL
HPS_USB_DATA[4] C8 inout 3.3-V LVTTL
HPS_USB_DATA[5] D4 inout 3.3-V LVTTL
HPS_USB_DATA[6] C7 inout 3.3-V LVTTL
HPS_USB_DATA[7] F4 inout 3.3-V LVTTL
HPS_USB_DIR E5 input 3.3-V LVTTL
HPS_USB_NXT D5 input 3.3-V LVTTL
HPS_USB_STP C5 output 3.3-V LVTTL