Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
u0|rst_controller_001|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
u0|rst_controller_001|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
u0|rst_controller_001 33 30 0 30 2 30 30 30 0 0 0 0 0
u0|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
u0|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
u0|rst_controller 33 31 0 31 1 31 31 31 0 0 0 0 0
u0|irq_mapper 6 28 2 28 32 28 28 28 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_010|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_010 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_009 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_008 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_007 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 22 1 2 1 21 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_006 22 0 0 0 21 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_005 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_004 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_003 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_002 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_001 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_cmd_width_adapter 126 3 0 3 103 3 3 3 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_rsp_width_adapter|uncompressor 44 4 0 4 35 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_rsp_width_adapter 108 3 0 3 121 3 3 3 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux_001|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux_001|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux_001 243 0 0 0 122 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux|arb|adder 44 22 0 22 22 22 22 22 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux|arb 15 0 4 0 11 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux 1323 0 0 0 131 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_010 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_009 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_008 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_007 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_006 124 4 2 4 241 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_005 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_004 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_003 124 4 2 4 241 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_002 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_001 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_010 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_009 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_008 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_007 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_006|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_006|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_006 243 0 0 0 122 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_005 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_004 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_003|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_003|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_003 243 0 0 0 122 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_002 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_001 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_demux_001 134 4 11 4 241 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|cmd_demux 143 121 2 121 1321 121 121 121 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter 105 3 5 3 103 3 3 3 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_burst_adapter 105 0 0 0 103 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|nios2_qsys_instruction_master_limiter 244 0 0 0 252 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|nios2_qsys_data_master_limiter 244 0 0 0 252 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_012|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_012 112 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_011|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_011 112 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_010|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_010 112 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_009|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_009 112 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_008|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_008 94 0 2 0 103 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_007|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_007 112 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_006|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_006 112 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_005|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_005 112 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_004|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_004 112 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_003|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_003 112 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_002|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
u0|mm_interconnect_0|router_002 112 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_001|the_default_decode 0 15 0 15 15 15 15 15 0 0 0 0 0
u0|mm_interconnect_0|router_001 112 0 6 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router|the_default_decode 0 15 0 15 15 15 15 15 0 0 0 0 0
u0|mm_interconnect_0|router 112 0 6 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_spi_spi_control_port_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_spi_spi_control_port_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_spi_spi_control_port_agent 308 39 48 39 328 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_pen_irq_n_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_pen_irq_n_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_pen_irq_n_s1_agent 308 39 48 39 328 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_busy_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_busy_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_busy_s1_agent 308 39 48 39 328 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|timer_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|timer_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|timer_s1_agent 308 39 48 39 328 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_agent_rdata_fifo 63 41 0 41 20 41 41 41 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_agent_rsp_fifo 134 39 0 39 93 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_agent 240 22 32 22 257 22 22 22 0 0 0 0 0
u0|mm_interconnect_0|key_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|key_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|key_s1_agent 308 39 48 39 328 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|lcd_reset_n_s1_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|lcd_reset_n_s1_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|lcd_reset_n_s1_agent 308 39 48 39 328 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|nios2_qsys_debug_mem_slave_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|nios2_qsys_debug_mem_slave_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|nios2_qsys_debug_mem_slave_agent 308 39 48 39 328 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sysid_qsys_control_slave_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sysid_qsys_control_slave_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|sysid_qsys_control_slave_agent 308 39 48 39 328 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|lt24_controller_0_avalon_slave_0_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|lt24_controller_0_avalon_slave_0_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|lt24_controller_0_avalon_slave_0_agent 308 39 48 39 328 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rsp_fifo 152 39 0 39 111 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent|uncompressor 44 1 0 1 42 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent 308 39 48 39 328 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|nios2_qsys_instruction_master_agent 194 39 89 39 144 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|nios2_qsys_data_master_agent 194 39 89 39 144 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_spi_spi_control_port_translator 95 22 44 22 56 22 22 22 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_pen_irq_n_s1_translator 111 6 29 6 70 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|touch_panel_busy_s1_translator 111 6 29 6 36 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|timer_s1_translator 95 22 44 22 55 22 22 22 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_translator 76 4 3 4 64 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|key_s1_translator 111 6 29 6 36 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|lcd_reset_n_s1_translator 111 6 29 6 70 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|nios2_qsys_debug_mem_slave_translator 111 5 19 5 82 5 5 5 0 0 0 0 0
u0|mm_interconnect_0|sysid_qsys_control_slave_translator 111 6 27 6 35 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|lt24_controller_0_avalon_slave_0_translator 111 38 27 38 69 38 38 38 0 0 0 0 0
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_translator 111 5 30 5 70 5 5 5 0 0 0 0 0
u0|mm_interconnect_0|nios2_qsys_instruction_master_translator 112 51 2 51 105 51 51 51 0 0 0 0 0
u0|mm_interconnect_0|nios2_qsys_data_master_translator 112 12 2 12 105 12 12 12 0 0 0 0 0
u0|mm_interconnect_0 376 0 0 0 353 0 0 0 0 0 0 0 0
u0|touch_panel_spi 25 0 0 0 20 0 0 0 0 0 0 0 0
u0|touch_panel_pen_irq_n 39 0 31 0 33 0 0 0 0 0 0 0 0
u0|touch_panel_busy 5 0 0 0 32 0 0 0 0 0 0 0 0
u0|timer 23 0 0 0 17 0 0 0 0 0 0 0 0
u0|sysid_qsys 3 20 2 20 32 20 20 20 0 0 0 0 0
u0|sdram|the_lt24_qsys_sdram_input_efifo_module 48 0 0 0 48 0 0 0 0 0 0 0 0
u0|sdram 48 1 1 1 40 1 1 1 16 0 0 0 0
u0|pll 2 0 0 0 3 0 0 0 0 0 0 0 0
u0|nios2_qsys|cpu 151 1 28 1 131 1 1 1 0 0 0 0 0
u0|nios2_qsys 151 0 0 0 130 0 0 0 0 0 0 0 0
u0|key 8 0 0 0 32 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r 13 0 1 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag_uart 38 10 23 10 34 10 10 10 0 0 0 0 0
u0|lt24_controller_0 37 1 18 1 20 1 1 1 0 0 0 0 0
u0|lcd_reset_n 38 31 31 31 33 31 31 31 0 0 0 0 0
u0 9 1 0 1 47 1 1 1 16 0 0 0 0