Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
u0|rst_controller_004|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_004|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_004 |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_003|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_003|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_003 |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_002|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_002|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_002 |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_001|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller_001 |
33 |
30 |
0 |
30 |
1 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
u0|irq_synchronizer_003 |
5 |
0 |
2 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|irq_synchronizer_002 |
5 |
0 |
2 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|irq_synchronizer_001 |
5 |
0 |
2 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|irq_synchronizer |
5 |
0 |
2 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|irq_mapper |
6 |
28 |
2 |
28 |
32 |
28 |
28 |
28 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_010|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_010 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_009 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_008 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_007 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_006 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_021|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_021|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_021|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_021 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_020|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_020|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_020|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_020 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_019|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_019|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_019|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_019 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_018|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_018|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_018|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_018 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_017|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_017|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_017|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_017 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_016|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_016|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_016|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_016 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_015|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_015|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_015|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_015 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_014|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_014|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_014|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_014 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_013|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_013|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_013|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_013 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_012|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_012|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_012|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_012 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_011|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_011|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_011|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_011 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_010|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_010|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_010|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_010 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_009|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_009|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_009|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_009 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_008|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_008|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_008|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_008 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_007|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_007|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_007|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_007 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_006|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_006|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_006|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_006 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_005|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_005|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_005|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_005 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_004|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_004|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_004|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_004 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_003|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_003|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_003|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_003 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_002|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_002|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_002|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_002 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_001|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_001|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_001|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser_001 |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser|clock_xer |
117 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|crosser |
119 |
2 |
0 |
2 |
113 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001 |
227 |
0 |
0 |
0 |
114 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux|arb|adder |
44 |
22 |
0 |
22 |
22 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux|arb |
15 |
0 |
4 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux |
1235 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_010 |
115 |
1 |
2 |
1 |
113 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_009 |
115 |
1 |
2 |
1 |
113 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_008 |
115 |
1 |
2 |
1 |
113 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_007 |
115 |
1 |
2 |
1 |
113 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_006 |
116 |
4 |
2 |
4 |
225 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_005 |
115 |
1 |
2 |
1 |
113 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_004 |
115 |
1 |
2 |
1 |
113 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_003 |
116 |
4 |
2 |
4 |
225 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_002 |
115 |
1 |
2 |
1 |
113 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_001 |
115 |
1 |
2 |
1 |
113 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux |
115 |
1 |
2 |
1 |
113 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_010 |
115 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_009 |
115 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_008 |
115 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_007 |
115 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_006|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_006|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_006 |
227 |
0 |
0 |
0 |
114 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_005 |
115 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_004 |
115 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003 |
227 |
0 |
0 |
0 |
114 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002 |
115 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_001 |
115 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux |
115 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_demux_001 |
126 |
4 |
11 |
4 |
225 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_demux |
135 |
121 |
2 |
121 |
1233 |
121 |
121 |
121 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_instruction_master_limiter |
228 |
0 |
0 |
0 |
236 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_data_master_limiter |
228 |
0 |
0 |
0 |
236 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_012|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_012 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_011|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_011 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_010|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_010 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_009|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_009 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_008|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_008 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_007|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_007 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_006|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_006 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_005|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_005 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_004|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_004 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_003|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_003 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_002|the_default_decode |
0 |
11 |
0 |
11 |
11 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_002 |
104 |
0 |
2 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_001|the_default_decode |
0 |
15 |
0 |
15 |
15 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_001 |
104 |
0 |
6 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router|the_default_decode |
0 |
15 |
0 |
15 |
15 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router |
104 |
0 |
6 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_spi_spi_control_port_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_spi_spi_control_port_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_spi_spi_control_port_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_spi_spi_control_port_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_pen_irq_n_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_pen_irq_n_s1_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_pen_irq_n_s1_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_pen_irq_n_s1_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_busy_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_busy_s1_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_busy_s1_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_busy_s1_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|timer_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|timer_s1_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|timer_s1_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|timer_s1_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory_s1_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory_s1_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory_s1_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|key_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|key_s1_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|key_s1_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|key_s1_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|lcd_reset_n_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|lcd_reset_n_s1_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|lcd_reset_n_s1_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|lcd_reset_n_s1_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_debug_mem_slave_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_debug_mem_slave_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_debug_mem_slave_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|lt24_controller_0_avalon_slave_0_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|lt24_controller_0_avalon_slave_0_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|lt24_controller_0_avalon_slave_0_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|lt24_controller_0_avalon_slave_0_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent_rsp_fifo |
144 |
39 |
0 |
39 |
103 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent|uncompressor |
36 |
1 |
0 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_agent |
292 |
39 |
48 |
39 |
304 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_instruction_master_agent |
178 |
39 |
81 |
39 |
136 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_data_master_agent |
178 |
39 |
81 |
39 |
136 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_spi_spi_control_port_translator |
87 |
22 |
36 |
22 |
56 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_pen_irq_n_s1_translator |
103 |
6 |
21 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|touch_panel_busy_s1_translator |
103 |
6 |
21 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|timer_s1_translator |
87 |
22 |
36 |
22 |
55 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory_s1_translator |
103 |
7 |
4 |
7 |
89 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|key_s1_translator |
103 |
6 |
21 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|lcd_reset_n_s1_translator |
103 |
6 |
21 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_debug_mem_slave_translator |
103 |
5 |
11 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|sysid_qsys_control_slave_translator |
103 |
6 |
19 |
6 |
35 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|lt24_controller_0_avalon_slave_0_translator |
103 |
38 |
19 |
38 |
69 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_avalon_jtag_slave_translator |
103 |
5 |
22 |
5 |
70 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_instruction_master_translator |
104 |
51 |
2 |
51 |
97 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_qsys_data_master_translator |
104 |
12 |
2 |
12 |
97 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0 |
378 |
0 |
0 |
0 |
362 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|touch_panel_spi |
25 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|touch_panel_pen_irq_n |
39 |
0 |
31 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|touch_panel_busy |
5 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|timer |
23 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|sysid_qsys |
3 |
18 |
2 |
18 |
32 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
u0|pll_0 |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory|the_altsyncram|auto_generated|mux2 |
259 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory|the_altsyncram|auto_generated|decode3 |
4 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory|the_altsyncram|auto_generated |
55 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory |
59 |
1 |
1 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|nios2_qsys|cpu |
151 |
1 |
28 |
1 |
115 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|nios2_qsys |
151 |
0 |
0 |
0 |
114 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|key |
6 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart|the_lt24_qsys_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
u0|lt24_controller_0 |
37 |
1 |
18 |
1 |
20 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|lcd_reset_n |
38 |
31 |
31 |
31 |
33 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
u0 |
7 |
1 |
0 |
1 |
24 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |