(---------------------------------------------------------------------)
(                                                                     )
(    Allegro Netrev Import Logic                                      )
(                                                                     )
(    Drawing          : a3_xd2.brd                                    )
(    Software Version : 17.0S003                                      )
(    Date/Time        : Sat Oct 17 22:36:43 2015                      )
(                                                                     )
(---------------------------------------------------------------------)


------ Directives ------------

Ripup etch:                  No
Ripup delete first segment:  No
Ripup retain bondwire:       No
Ripup symbols:               Always
Missing symbol has error:    No
DRC update:                  Yes
Schematic directory:         '../netlist'
Design Directory:            '.'
Old design name:             'D:/_doc/HP_Agilent_Keysight/3458A/a3_xd2/pcb/a3_xd2.brd'
New design name:             'D:/_doc/HP_Agilent_Keysight/3458A/a3_xd2/pcb/a3_xd2.brd'

CmdLine: netrev -$ -i ../netlist -y 1 -z -q netrev_constraint_report.xml D:/_doc/HP_Agilent_Keysight/3458A/a3_xd2/pcb/#Taaaaah14568.tmp

------ Preparing to read pst files ------

Starting to read ../netlist/pstchip.dat 
   Finished reading ../netlist/pstchip.dat (00:00:00.02)
Starting to read ../netlist/pstxprt.dat 
   Finished reading ../netlist/pstxprt.dat (00:00:00.00)
Starting to read ../netlist/pstxnet.dat 
   Finished reading ../netlist/pstxnet.dat (00:00:00.00)

------ Oversights/Warnings/Errors ------


#1   WARNING(SPMHNI-192): Device/Symbol check warning detected. [help]

ERROR(SPMHNI-196): Symbol 'LED_1206' for device 'ZNR_LED_1206_ZNR' has extra pin 'C'.

ERROR(SPMHNI-196): Symbol 'LED_1206' for device 'ZNR_LED_1206_ZNR' has extra pin 'A'.

ERROR(SPMHNI-195): Symbol 'LED_1206' for device 'ZNR_LED_1206_ZNR' is missing pin '1'.

ERROR(SPMHNI-195): Symbol 'LED_1206' for device 'ZNR_LED_1206_ZNR' is missing pin '2'.

------ Library Paths ------
MODULEPATH =  . 
           C:/Cadence/SPB_17.0/share/local/pcb/modules 

PSMPATH =  ../lib 
           . 
           symbols 
           .. 
           ../symbols 
           C:/Cadence/SPB_17.0/share/local/pcb/symbols 
           C:/Cadence/SPB_17.0/share/pcb/pcb_lib/symbols 
           C:/Cadence/SPB_17.0/share/pcb/allegrolib/symbols 

PADPATH =  ../lib 
           . 
           symbols 
           .. 
           ../symbols 
           C:/Cadence/SPB_17.0/share/local/pcb/padstacks 
           C:/Cadence/SPB_17.0/share/pcb/pcb_lib/symbols 
           C:/Cadence/SPB_17.0/share/pcb/allegrolib/symbols 


------ Summary Statistics ------


netrev run on Oct 17 22:36:43 2015
   DESIGN NAME : 'A3_XD2'
   PACKAGING ON Feb  9 2015 06:09:36

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

 No error detected
 No oversight detected
  1 warnings detected

cpu time      0:00:22
elapsed time  0:00:00