This section lists the STATUS and CONTROL registers for I/O path names, interfaces, and pseudo select code 32.
All 8-bit (byte-width) registers are described using 8-column tables like the one shown below. Bit 7 is the most-significant bit and bit 0, the least-significant bit.
STATUS Register 11 | Termination status for outbound TRANSFER |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | TRANSFER Active | TRANSFER Aborted | TRANSFER Error | Device Termination | Byte Count | Record Count | 0 |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
The value field below each bit gives the weighting of that bit when it has a defined use. These values help you convert the binary bit values to decimal values when calculating the total register value. However, if a bit is defined as 0 or not used, you should ignore the value field. For example, in the table above, bits 7 and 0 are both defined as 0, so the value = 128 and value = 1 fields have no effect on the total register value.
All 16-bit (word-width) registers are shown as two 8-column tables with the most-significant byte above the least-significant byte.
STATUS Register 0 | 0 = Invalid I/O path name
1 = I/O path name assigned to a device 2 = I/O path name assigned to a data file 3 = I/O path name assigned to a buffer 4 = I/O path name assigned to an HP-UX special file |
STATUS Register 1 | Interface select code |
STATUS Register 2 | Number of devices |
STATUS Register 3 | Address of 1st device |
If assigned to more than one device, the addresses of the other devices are available starting in STATUS Register 4.
STATUS Register 1 | File type = 3 |
STATUS Register 2 | Device selector of mass storage device
(not supported for HFS on BASIC/UX) |
STATUS Register 3 | Number of records |
STATUS Register 4 | Bytes per record = 256 |
STATUS Register 5 | Current record |
STATUS Register 6 | Current byte within record |
STATUS Register 9 | File I/O buffering in use Useful for BASIC/UX only. BASIC/WS always returns 0.) |
CONTROL Register 9 | Set file I/O buffer. Useful for BASIC/UX only. BASIC/WS allows you to write to this register but no action is taken. Writing zero (0) enables buffering. Writing one (1) disables buffering. |
CONTROL Register 10 | In BASIC/DOS, writing a 1 to this register writes the pending buffer
to the disk file and updates the directory entry for the file. However, this
command has no effect on the buffering mode as defined by Control Register
9.
Note that BASIC/WS and BASIC/UX allow this command but perform no action. |
STATUS Register 1 | File type = 2 |
STATUS Register 2 | Device selector of mass storage device
(not supported for HFS on BASIC/UX) |
STATUS Register 3 | Number of defined records |
STATUS Register 4 | Defined record length |
STATUS Register 5 | Current record |
CONTROL Register 5 | Set record |
STATUS Register 6 | Current byte within record |
CONTROL Register 6 | Set byte within record |
STATUS Register 7 | EOF record |
CONTROL Register 7 | Set EOF record |
STATUS Register 8 | Byte within EOF record |
CONTROL Register 8 | Set byte within EOF record |
STATUS Register 9 | File I/O buffering in use (Useful for BASIC/UX only. BASIC/WS returns 0.) |
CONTROL Register 9 | Set file I/O buffer. BASIC/WS and BASIC/DOS allow you to write to this register but no action is taken. Writing zero (0) enables buffering. Writing one (1) disables buffering. |
CONTROL Register 10 | In BASIC/DOS, writing a 1 to this register writes the pending buffer
to the disk file and updates the directory entry for the file. However, this
command has no effect on the buffering mode as defined by Control Register
9.
Note that BASIC/WS and BASIC/UX allow this command but perform no action. |
STATUS Register 1 | File type = 4 |
STATUS Register 2 | Device selector of mass storage device (not supported for HFS on BASIC/UX) |
STATUS Register 3 | Number of defined records |
STATUS Register 4 | Defined record length (fixed record length = 1) |
STATUS Register 5 | Current record |
CONTROL Register 5 | Set record |
STATUS Register 6 | Current byte within record |
CONTROL Register 6 | Set byte within record |
STATUS Register 7 | EOF record |
CONTROL Register 7 | Set EOF record |
STATUS Register 8 | Byte within EOF record |
CONTROL Register 8 | Set byte within EOF record |
STATUS Register 9 | File I/O buffering in use (Useful for BASIC/UX only. BASIC/WS returns
0.)
|
CONTROL Register 9 | Set file I/O buffer. BASIC/WS allows you to write to this register but no action is taken. Writing zero (0) enables buffering. Writing one (1) disables buffering. |
CONTROL Register 10 | In BASIC/DOS, writing a 1 to this register writes the pending buffer
to the disk file and updates the directory entry for the file. However, this
command has no effect on the buffering mode as defined by Control Register
9.
Note that BASIC/WS and BASIC/UX allow this command but perform no action. |
STATUS Register 1 | Buffer type (1=named, 2=unnamed) |
STATUS Register 2 | Buffer size in bytes |
STATUS Register 3 | Current fill pointer |
CONTROL Register 3 | Set fill pointer |
STATUS Register 4 | Current number of bytes in buffer |
CONTROL Register 4 | Set number of bytes |
STATUS Register 5 | Current empty pointer |
CONTROL Register 5 | Set empty pointer |
STATUS Register 6 | Interface select code of inbound TRANSFER |
STATUS Register 7 | Interface select code of outbound TRANSFER |
STATUS Register 8 | If non-zero, inbound TRANSFER is continuous |
CONTROL Register 8 | Cancel continuous mode inbound TRANSFER if zero |
STATUS Register 9 | If non-zero, outbound TRANSFER is continuous |
CONTROL Register 9 | Cancel continuous mode outbound TRANSFER if zero |
STATUS Register 10 | Termination status for inbound TRANSFER |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | TRANSFER Active | TRANSFER Aborted | TRANSFER Error | Device Termination | Byte Count | Record Count | Match Character |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 11 | Termination status for outbound TRANSFER |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | TRANSFER Active | TRANSFER Aborted | TRANSFER Error | Device Termination | Byte Count | Record Count | 0 |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 12 | Total number of bytes transferred by last inbound TRANSFER |
STATUS Register 13 | Total number of bytes transferred by last outbound TRANSFER |
STATUS Register 1 | 1 = I/O path is assigned to an HP-UX pipe |
STATUS Register 2 | 0 = inbound pipe
1 = outbound pipe 2 = bidirectional pipe |
STATUS Register 0 | Current print position (column) | ||||||||||||||||||||||||
CONTROL Register 0 | Set print position (column). See also TAB and TABXY. | ||||||||||||||||||||||||
STATUS Register 1 | Current print position (line) | ||||||||||||||||||||||||
CONTROL Register 1 | Set print position (line). See also TABXY. | ||||||||||||||||||||||||
STATUS Register 2 | Insert-character mode | ||||||||||||||||||||||||
CONTROL Register 2 | Set insert character mode if non-0. Error 713 is given if a window number is specified instead of a select code on BASIC/UX. | ||||||||||||||||||||||||
STATUS Register 3 | Number of lines "above screen". | ||||||||||||||||||||||||
CONTROL Register 3 | Undefined | ||||||||||||||||||||||||
STATUS Register 4 | Display functions mode | ||||||||||||||||||||||||
CONTROL Register 4 | Set display functions mode if non-0. To perform the same function, use the statement DISPLAY FUNCTIONS ON/OFF. | ||||||||||||||||||||||||
STATUS Register 5 | Returns the CRT alpha color value set (or default). This does not reflect changes due to printing CHR$(x), where 136<x>143. | ||||||||||||||||||||||||
CONTROL Register 5 | Set default alpha color or gray value
For Alpha Displays:
For Bit-Mapped Displays: Values 0 through 255 which correspond to the graphics pens. The values are treated as MOD 2^n where n is the number of display planes. For Gray-Scale Displays: the value corresponds to a different intensity of gray. CONTROL CRT,5;n sets the values of the CRT registers 15, 16, and 17, but the converse is not true. That is, STATUS CRT,5 may not accurately reflect the CRT state if CONTROL 15, 16, and/or 17 have been executed. Note that to perform the same function as CONTROL CRT,5;n, you can use the ALPHA PEN statement. |
STATUS Register 6 | ALPHA ON flag. Error 713 is given if a window number is specified instead of a select code on BASIC/UX. |
CONTROL Register 6 | Undefined. Error 713 is given if a window number is specified instead of a select code on BASIC/UX. |
STATUS Register 7 | GRAPHICS ON flag. Error 713 is given if a window number is specified instead of a select code on BASIC/UX. |
CONTROL Register 7 | Undefined. Error 713 is given if a window number is specified instead of a select code on BASIC/UX. |
STATUS Register 8 | Display line position (column). Error 713 is given if a window number is specified instead of a select code on BASIC/UX. |
CONTROL Register 8 | Set display line position(column). See also TAB.
Error 713 is given if a window number is specified instead of a select code on BASIC/UX. |
STATUS Register 9 | Screenwidth (number of characters). Also available in the SYSTEM$("CRT ID") function result. |
CONTROL Register 9 | Undefined |
STATUS Register 10 | Cursor-enable flag. Error 713 is given if a window number is specified instead of a select code on BASIC/UX. |
CONTROL Register 10 | Cursor-enable:
|
STATUS Register 11 | CRT character mapping flag |
CONTROL Register 11 | Disable CRT character mapping (if non-0). This is valid only for non-bit-mapped displays. |
STATUS Register 12 | Key labels display mode. Error 713 is given if a window number is specified instead of a select code on BASIC/UX. |
CONTROL Register 12 | Set key labels display mode:
|
STATUS Register 13 | CRT height (number of lines to be used for alpha display). |
CONTROL Register 13 | Set CRT height (must be >9). Alternately use the ALPHA HEIGHT statement. |
STATUS Register 14 | Display replacement rule currently in effect. For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
CONTROL Register 14 | Set display replacement rule (with bit-mapped alpha displays only). (BASIC/WS
only)
This register is not processed for the 9836C display, nor for the Model 362/382 internal displays. Any updates made to this register are ignored for those displays.
It is strongly recommended that you do not change the default display replacement rule.
|
STATUS Register 15 | Return the value set (or the default) for the color in the
PRINT/DISP area.
This does not reflect changes due to printing CHR$(x), where 136<x<143.
|
||||||||||||||||
CONTROL Register 15 | Set PRINT/DISP color (or use the PRINT PEN statement).
Similar to CRT control register 5 but specific to CRT PRINT/DISP areas; that is, it does not affect the areas covered by CRT registers 16 and 17.
|
||||||||||||||||
STATUS Register 16 | Return the value set (or the default) for the softkey label color.
Error 713 is given if a window number is specified instead of a select code on BASIC/UX.
|
||||||||||||||||
CONTROL Register 16 | Set key labels color (or use the KEY LABELS PEN statement). Similar to
CRT control register 5 but
only affects the softkey labels. Does not affect the areas covered by CRT registers 15 and 17. Error 713 is given if a window number is specified instead of a select code on BASIC/UX.
|
||||||||||||||||
STATUS Register 17 | Return the value set (or the default) for the color of the "non-enhance"
area.
This includes the keyboard entry line, runlight, system message line, annunciators, and edit screen. Error 713 is given if a window number is specified instead of a select code on BASIC/UX.
|
||||||||||||||||
CONTROL Register 17 | Set "non-enhance" color (or use the KBD LINE PEN statement). This includes
the keyboard entry line, runlight, system message line, annunciators, and
edit screen. Similar to CRT control register 5 but does not affect the areas
covered by CRT control registers 15 and 16. Error 713 is given if a window
number is specified instead of a select code on BASIC/UX.
|
||||||||||||||||
STATUS Register 18 | Read the alpha write-enable mask.
|
||||||||||||||||
CONTROL Register 18 | Set alpha write-enable mask to a bit pattern (or use the SET ALPHA MASK
statement). When running BASIC/UX in the X Window environment, this CONTROL
register is not supported. Error 713 is given if a window number is
specified instead of a select code on BASIC/UX.
|
||||||||||||||||
STATUS Register 19 | Returns the maximum value for the ALPHA MASK argument. | ||||||||||||||||
CONTROL Register 19 | Undefined. | ||||||||||||||||
STATUS Register 20 | Read the alpha display-enable mask. Not supported when running BASIC/UX
in X Windows.
Error 713 is given if a window number is specified instead of a select code on BASIC/UX.
|
||||||||||||||||
CONTROL Register 20 | Set alpha display-enable mask to a bit pattern (or use the SET DISPLAY
MASK statement).
Not supported when running BASIC/UX in X Windows. Error 713 is given if a window number is specified instead of a select code on BASIC/UX.
|
||||||||||||||||
STATUS Register 21 | Active CRT binary id!entity. See CONTROL register 21 for a table of CRT
binary identification codes.
|
||||||||||||||||
CONTROL Register 21 | Specify which loaded CRT binary BASIC will attempt to activate. Each
CRT binary is represented by one of the following values:
If 0 is sent to CONTROL register 21, BASIC searches all the loaded binaries in a default order and activates the first one found that is compatible with the installed hardware. The default search order is CRTD, then CRTB, then CRTA. Sending a new value to CONTROL register 21 effectively initializes the alpha display and executes GINIT and PLOTTER IS CRT, INTERNAL . BASIC/UX does not support switching between non-bit-mapped and bit-mapped displays, but the initialization is still done. Error 713 is given if a window number is specified instead of a select code on BASIC/UX. |
||||||||||||||||
STATUS Register 22 | Undefined (BASIC/UX in X-Windows only). | ||||||||||||||||
CONTROL Register 22 | Raises a window to the top of the window stack if non-zero; pushes a window to the bottom of the stack if zero (BASIC/UX in X-Windows only). | ||||||||||||||||
STATUS Register 23 | Returns terminal compatibility mode. (BASIC/UX in terminal mode. Returns 0 for BASIC/UX in other modes.) | ||||||||||||||||
CONTROL Register 23 | Sets terminal compatibility mode. (BASIC/UX in terminal mode. Returns 0 for BASIC/UX in other modes.) |
STATUS Register 0 | CAPS LOCK flag |
CONTROL Register 0 | Set CAPS LOCK if non-0 |
STATUS Register 1 | PRINTALL flag |
CONTROL Register 1 | Set PRINTALL if non-0 |
STATUS Register 2 | Function key menu |
CONTROL Register 2 | Function key menu:
|
STATUS Register 3 | Undefined |
CONTROL Register 3 | Set auto-repeat interval. If 1 through 255, repeat interval in milliseconds is 10 times this value. 256 = turn off auto-repeat. (Default at power-on or SCRATCH A is 40ms.) For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
STATUS Register 4 | Undefined |
CONTROL Register 4 | Set delay before auto-repeat. If 1 through 256, delay in milliseconds is 10 times this value. (Default at power-on or SCRATCH A is 300ms.) For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
STATUS Register 5 | KBD$ buffer overflow register, 1 = overflow. Register is reset when read. |
CONTROL Register 5 | Undefined |
STATUS Register 6 | Typing aid expansion overflow register, 1 = overflow. Register is reset when read. |
CONTROL Register 6 | Undefined |
STATUS Register 7 | Interrupt Status |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
0 | 0 | 0 | INITIALIZE Timeout Interrupt Disabled | Reserved For Future Use | Reserved For Future Use | RESET Key Interrupt Disabled | Keyboard and Knob Interrupt Disabled |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
CONTROL Register 7 | Interrupt Disable Mask |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Not Used | INITIALIZE Timeout | Reserved For Future Use | Reserved For Future Use | RESET Key | Keyboard and Knob | ||
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 8 | Keyboard language jumper |
0-US ASCII | 7-United Kingdom | 14-Latin (Spanish) |
1-French | 8-Canadian French | 15-Danish |
2-German | 9-Swiss French | 16-Finnish |
3-Swedish | 10-Italian | 17-Norwegian |
4-Spanish | 11-Belgian | 18-Swiss French1 |
5-Katakana | 12-Dutch | 19-Swiss German1 |
6-Canadian English | 13-Swiss German | 20-Kanji (Japanese) |
1 See also SYSTEM$("KEYBOARD LANGUAGE") which requires the LEX binary. Note that the STATUS statement when used with this register does not require the LEX binary.
CONTROL Register 8 | Undefined |
STATUS Register 9 | Keyboard Type
For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Internal Use | Internal Use | 1=HIL Keyboard Interface 0=non-HIL | 1=No Keyboard 0=Key-board Present | 1=n-Key Rollover
0=2 or less rollover |
0 | 1=98203C Keyboard
0=Other Keyboard |
1=98203A Keyboard 0=Other Keyboard |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
Bits 5, 1, and 0 of STATUS Register 9 and the following table can be used to determine the Keyboard Type.
Bit 5 | Bit 1 | Bit 0 | Keyboard Type |
---|---|---|---|
0 | 0 | 0 | HP 98203B or built-in |
0 | 0 | 1 | HP 98203A |
1 | 0 | 0 | ITF (such as the HP 46020A and 46021A) |
1 | 1 | 0 | HP 98203C |
CONTROL Register 9 | Undefined |
STATUS Register 10 | Status at Last Knob Interrupt |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | 0 | CTRL Key
Pressed |
SHIFT Key
Pressed |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
Note that bit 1 is always 0 for keyboards connected to an HP-HIL interface, and with all HP-HIL mice and knobs (e.g. HP 46083A Rotary Control Knob, HP 46085 Control Dials, and HP 98203C Keyboard Knob).
For BASIC/UX information on this register, see the HP BASIC Interface Reference.
CONTROL Register 10 | Undefined |
STATUS Register 11 | 0=horizontal-pulse mode; 1=all-pulse mode. |
CONTROL Register 11 | Set knob pulse mode (0 is default). See the knob discussion in the "Porting to 3.0" chapter of HP BASIC Porting and Globalization. For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
STATUS Register 12 | "Pseudo-EOI for CTRL-E " flag |
CONTROL Register 12 | Enable pseudo-EOI for CTRL-E if non-0 |
STATUS Register 13 | Katakana flag |
CONTROL Register 13 | Set Katakana if non-0 |
STATUS Register 14 | Numbering of softkeys on ITF keyboard:
0 -- [f1] is key number 1 (default); 1 -- [f1] is key number 0; |
CONTROL Register 14 | Softkey numbering on ITF keyboard (see STATUS Register 14 description) |
STATUS Register 15 | Currently in 98203 keyboard compatibility mode:
0--OFF (default) 1--ON |
CONTROL Register 15 | Turns "98203 keyboard compatibility mode" on (<>0) and off (=0).
(See the chapter "Porting to Series 300" in the HP BASIC Porting and
Globalization manual for further information about using this mode.)
Note that instead of using the CONTROL register 15 statement you can use
the KBD CMODE statement to turn the "98203 keyboard compatibility mode" ON
and OFF.
For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
STATUS Register 16 | Returns the enabled/disabled status of the up and down arrow keys, [Prev], [Next], and [diagional home] (both shifted and un-shifted for all of these keys). If the status value is 1 it means these keys are deactivated. Note that the default value is 0. |
CONTROL Register 16 | Allows you to disable or re-enable the display scrolling keys mentioned for STATUS Register 16. This prevents accidental scrolling of the display screen. Executing a 1 with the CONTROL statement deactivates the print scrolling keys and a 0 activates them. |
STATUS Register 17 | Automatic menu switching:
1 -- enabled (default) 0 -- disabled |
CONTROL Register 17 | Automatic menu switching:
<>0-- enable 0 -- disable This register controls whether a system with an ITF keyboard will switch to (from) the User 2 Menu automatically on entering (leaving) EDIT mode. |
STATUS Register 24 | Two-byte character input mode activation status. (BASIC/UX always returns
0.)
|
CONTROL Register 24 | Enables/disables two-byte character input. Setting this register has an effect only if a two-byte INPUT binary is loaded. See STATUS register 24 for details. (BASIC/UX ignores data sent.) |
STATUS Register 25 | Two-byte character input switch key enable status (BASIC/UX returns 0
only). The two-byte switch key toggles the keyboard between one- and two-byte
character input.
Not affected by BASIC reset. |
CONTROL Register 25 | Enables/disables two-byte switch key (BASIC/UX ignores data sent). Setting
this register has an effect only if a two-byte INPUT binary is loaded. See
STATUS register 25 for details.
|
STATUS and CONTROL Registers 26-30 | Reserved for use with the Japanese INPUT binary. Refer to the Using Japanese with HP BASIC manual for details. |
STATUS Register 0 | Card identification = 1 |
CONTROL Register 0 | Reset interface if non-zero |
STATUS Register 1 | Interrupt and DMA Status |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Interrupts Enabled | Interrupt Requested | Interrupt Level | 0 | 0 | DMA Chan 1 Enabled1 | DMA Chan 0 Enabled1 | |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
1Always 0 on HP BASIC/UX 700.
CONTROL Register 1 | Serial Poll Response Byte |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Device Dependent Status | SRQ
1=I did it 0=I didn't |
Device Dependent Status |
|||||
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 2 | Busy Bits |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | Reserved For Future Use | Hand-hake In Progress | Interrupts Enabled | TRANSFER In Progress |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
CONTROL Register 2 | Parallel Poll Response Byte |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
DIO8 1=True | DIO7 1=True | DIO6 1=True | DIO5 1=True | DIO4 1=True | DIO3 1=True | DIO2 1=True | DIO1 1=True |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 3 | Controller Status and Address |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
System
Controller |
Active
Controller |
0 | Primary Address of HP-IB Interface |
||||
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
CONTROL Register 3 | Set My Address |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Not Used | Primary Address |
||||||
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 4 | Interrupt Status |
Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 |
---|---|---|---|---|---|---|---|
Active Controller | Parallel Poll Configuration Change | My Talk Address Received | My Listen Address Received | EOI Received | SPAS | Remote/ Local Change | Talker/ Listener Address Change |
value= -32 768 | value=16 384 | value=8 192 | value=4 096 | value= 2048 | value= 1024 | Value=512 | value=256 |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Trigger Received | Hand- shake Error1 | Unrecog- nized Universal Command1 | Secondary Command While Addressed1 | Clear Received | Unrecog- nized Addressed Command1 | SRQ Received | IFC Received |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
1Always 0 on HP BASIC/UX 700.
CONTROL Register 4 | Writing anything to this register releases NDAC holdoff. If non-zero, accept last secondary address as valid. If zero, don't accept last secondary address (stay in LPAS or TPAS state). Not supported on HP BASIC/UX 700. |
STATUS Register 5 | Interrupt Enable Mask |
Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 |
---|---|---|---|---|---|---|---|
Active Controller | Parallel Poll Con- figuration Change | My Talk Address Received | My Listen Address Received | EOI Received | SPAS | Remote/ Local Change | Talker/ Listener Address Change |
value= -32 768 | value=16 384 | value=8 192 | value=4 096 | value= 2 048 | value= 1 024 | value=512 | value=256 |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Trigger Received | Hand- shake Error1Interrupt condition not supported on HP BASIC/UX 700. | Unrecog- nized Universal Command1 | Secondary Command While Addressed1 | Clear Received | Unrecog- nized Addressed Command1 | SRQ Received | IFC Received |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
1Interrupt condition not supported on HP BASIC/UX 700.
CONTROL Register 5 | Parallel Poll Response Mask |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Not Used | Not Used | Not Used | Uncon- figure | Logic Sense | Data Bits Used for Response | ||
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 6 | Interface Status |
Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 |
---|---|---|---|---|---|---|---|
REM | LLO | ATN True | LPAS | TPAS | LADS | TADS | * |
value=-32 768 | value=16 384 | value=8 192 | Value=4 096 | Value=2 048 | Value=1 024 | value=512 | Value=256 |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
System Controller | Active Controller | 0 | Primary Address of Interface |
||||
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
*Least-significant bit of last address recognized. Not supported on HP BASIC/UX 700.
STATUS Register 7 | Bus Control and Data Lines |
Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit8 |
---|---|---|---|---|---|---|---|
ATN True | DAV True | NDAC1 True | NRFD1 True | EOI True | SRQ2 True | IFC True | REN True |
value=-32 768 | value=16 384 | value=8 192 | value=4 096 | value=2 048 | value=1 024 | value=512 | value=256 |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
DIO8 | DIO7 | DIO6 | DIO5 | DIO4 | DIO3 | DIO2 | DIO1 |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
1Only if currently Addressed to Talk, otherwise not valid.
2Only if currently Active Controller, otherwise not valid.
Lower eight bits (data lines) always return 0 on HP BASIC/UX 700.
Interrupt Enable Register (ENABLE INTR)
Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit8 |
---|---|---|---|---|---|---|---|
Active Controller | Parallel Poll Con- figuration Change | My Talk Address Received | My Listen Address Received | EOI Received | SPAS | Remote/ Local Change | Talker/ Listener Address Change |
value= -32 768 | value= 16 384 | value=8 192 | value=4 096 | value= 2 048 | value= 1 024 | value=512 | value=256 |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Trigger Received | Hand- shake Error1 | Unrecog- nized Universal Command1 | Secondary Command While Addressed1 | Clear Received | Unrecog- nized Addressed Command1 | SRQ Received | IFC Received |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
1 Not supported on HP BASIC/UX 700.
STATUS Register 255 | Lock and I/O Mode |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Not used | Reserved for future use | ENTER buffering | I/O-map driver | Interface lock | |||
Value=128 | Value=64 | Value=32 | Value=16 | Value=8 | Value=4 | Value=2 | Value=1 |
HP BASIC/WS and HP BASIC/DOS always return the value 3.
Burst mode (HP BASIC/UX 300/400) returns the value 3: interface locked with an I/O-mapped driver.
Bit 1 (map or burst) is not supported on HP BASIC/UX 700.
Bit 2 (buffer mode) is supported only on HP BASIC/UX 700.
CONTROL Register 255 | Lock and I/O Mode |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Not Used |
Reserved for future use |
ENTER buffering | I/O-map driver | Interface lock | |||
Value=128 | Value=64 | Value=32 | Value=16 | Value=8 | Value=4 | Value=2 | Value=1 |
HP BASIC/WS and HP BASIC/DOS always set the value 3, regardless of the parameter in the program.
HP BASIC/UX 300/400 programs must set bit 0 if bit 1 is set (burst mode).
Bit 1 (map or burst) is not supported on HP BASIC/UX 700.
Bit 2 (buffer mode) is supported only on HP BASIC/UX 700.
Most Control registers accept values in the range of zero through 255. Some registers accept only specified values as indicated, or higher values for baud rate settings. Values less than zero are not accepted. Higher-order bits not needed by the interface are discarded if the specified value exceeds the valid range.
Reset value is the default value used by the interface after a reset or power-up until the value is overridden by a CONTROL statement.
See the HP BASIC Interface Reference for "Modifications to RS-232 and Datacomm Registers."
STATUS Register 0 | Card Identification
Value returned: 2 indicates a Series 700 built-in RS-232, or a 98626 (if 130 is returned, the Remote jumper wire has been removed from the interface card); 66 indicates a 98644 (194 if the Remote jumper has been removed). |
CONTROL Register 0 | Interface Reset
Any value from 1 through 255 resets the card. Execution is immediate; any data transfers in process are aborted and any buffered data is destroyed. A value of 0 causes no action. |
STATUS Register 1 | Interrupt Status
Bit 7 set: Interface hardware interrupt to CPU enabled. Bit 6 set: Card is requesting interrupt service. Bits 5&4: 00 - Interrupt Level 3 01 - Interrupt Level 4 10 - Interrupt Level 5 11 - Interrupt Level 6 Bits 5 and 4 cannot be controlled by the programmer on a Series 700 computer. Bits 3-0 Not used. |
CONTROL Register 1 | Transmit BREAK Any non-zero value sends a 400 millisecond BREAK on the serial line. For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
STATUS Register 2 | Interface Activity Status Bit 7 thru 3 are not used. Bit 2 set: Handshake
in progress. This occurs only during multi-line function calls.
Bit 1 set: Firmware interrupts enabled (ENABLE INTR active for this select code). Bit 0 set:TRANSFER in Progress. For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
STATUS Register 3 | Current Baud Rate
Returns one of the values listed under CONTROL Register 3. |
CONTROL Register 3 | Set New Baud Rate
Use any one of the following values:
From 25 to 86400, the value will be rounded. Any value outside this range gives an error. |
STATUS Register 4 | Current Character Format
See CONTROL Register 4 for function of individual bits. |
CONTROL Register 4 | Set Character Format
1CONTROL register 15 also sets the handshake mode. Register 15 has more capability; these bits are provided for backward compatibility only. Changing these bits in register 4 also affects Register 15, and vice-versa. 2Parity sense valid only if parity is enabled (bit3=1). If parity is disabled, parity sense is ignored, no parity bit is transmitted, and no received parity bit is expected. 3If 2 stop bits are requested, and the character length is 5 bits, then only 1.5 stop bits are transmitted.
1Parity sense valid only if parity is enabled (bit 3=1). If parity is disabled, parity sense is meaningless. 2These bits correspond to equivalent switch settings on the HP 98626 and HP 98644| serial interface cards. A 1 is the same as set.
1Parity sense valid only if parity is enabled (bit 3=1). If parity is disabled, parity sense is meaningless. Bits 6 and 7 are reserved for future use.
|
STATUS Register 5 | Current Status of Modem Control Lines
Returns CURRENT line state values. See CONTROL Register 5 for function of each bit.
|
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CONTROL Register 5 | Set Modem Control Line States
For HP BASIC/UX 300/400 and HP BASIC/WS, sets Modem Control lines or interface state as follows:
For HP BASIC/UX 700, sets Modem Control lines or interface state as follows:
|
STATUS Register 6 | Data In
Reads character from input buffer. Buffer contents is not destroyed, but bit 0 of STATUS Register 10 is cleared. Not supported on HP BASIC/UX 700. |
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CONTROL Register 6 | Data Out
Sends character to transmitter holding register. This register is sometimes used to transmit protocol control characters or other characters without using OUTPUT statements. Modem control lines are not affected. Not supported on HP BASIC/UX 700. |
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STATUS Register 7 | Optional Receiver/Driver Status Returns current value of optional circuit
drivers or receivers as follows:
|
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CONTROL Register 7 | Set New Optional Driver States Sets (bit=1) or clears (bit=0) optional
circuit drivers as follows:
|
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STATUS Register 8 | Current Interrupt Enable Mask Returns value of interrupt mask associated
with most recent ENABLE INTR statement. Bit functions are as follows:
|
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STATUS Register 9 | Cause of Current Interrupt
Returns cause of interrupt as follows:
|
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STATUS Register 10 | UART Status
Bit set indicates UART status or detected error as follows:
|
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STATUS Register 11 | Modem Status
Bit set indicates that the specified modem line or condition is active.
|
STATUS Register 12 | Modem Handshake Control
(not supported on BASIC/UX) |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
Carrier Detect Disable1 | 0 | Data Set Ready Disable2 | Clear to Send Disable3 | 0 | 0 | 0 | 0 |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
10 = Wait for Carrier Detect on Enter Operations; 1=Don't wait. BASIC/UX supports bits 7 and 4 in combination only
20 = Wait for Data Set Ready on Enter and Output Operations; 1=Don't wait. BASIC/WS only.
30 = Wait for Clear to Send on Output Operations; 1=Don't wait. BASIC/UX supports bits 7 and 4 in combination only.
CONTROL Register 12 | Modem Handshake Control
(not supported on BASIC/UX) |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Carrier Detect Disable1 | Not Used | Data Set Ready Disable2 | Clear to Send Disable3 | Not Used | Not Used | Not Used | Not Used |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
10=Wait for Carrier Detect on Enter Operations; 1=Don't wait. BASIC/UX supports bits 7 and 4 in combination only
20=wait for Data Set Ready on Enter and Output Operations; 1=Don't wait. BASIC/WS only.
30=Wait for Clear to Send on Output Operations; 1=Don't wait. BASIC/UX supports bits 7 and 4 in combination only.
STATUS Register 13 | Read "SCRATCH A default" baud rate
Returns the baud rate that will be restored whenever SCRATCH A is executed (same bit-definitions as STATUS register 3). For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
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CONTROL Register 13 | Set "SCRATCH A default" baud rate
Sets both the "current" and the "default" baud rate that will be restored whenever SCRATCH A is executed (same bit-definitions as CONTROL register 3). Default value in this register is 9600 baud. For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
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STATUS Register 14 | Read "SCRATCH A default" character format
Returns the character format parameters that will be restored whenever SCRATCH A is executed (same bit-definitions as STATUS register 4). For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
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CONTROL Register 14 | Set "SCRATCH A default" character format
Sets both the "current" and the "default" character format parameters that will be restored whenever SCRATCH A is executed (same bit-definitions as CONTROL register 4). Default value in this register specifies a character format of 8 bits/character, 1 stop bit, and parity disabled. |
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STATUS Register 15 | Read Handshake and Pacing
Returns one of the values listed for CONTROL register 15. Supported on BASIC/UX 700 only. |
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CONTROL Register 15 | Set Handshake and Pacing
The following mutually-exclusive modes are available. Note that Disable and Xon/Xoff are also in register 4. Changing those values in Register 15 also affects bits 6&7 of Register 4, and vice-versa. Supported on BASIC/UX 700 only.
|
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STATUS Register 16 | Read "SCRATCH A default" handshake and pacing
Returns the handshake mode that will be restored whenever SCRATCH A is executed. Same bit definitions as STATUS register 15. Supported on BASIC/UX 700 only. |
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CONTROL Register 16 | Set "SCRATCH A default" character format
Sets both the current and the default handshake mode that will be restored whenever SCRATCH A is executed. Same bit definitions as CONTROL register 15. Note that register 14 has no effect on the "SCRATCH A default" handshake mode. Supported on BASIC/UX 700 only. |
Interrupt Enable Register | (ENABLE INTR) |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Not Used |
Modem
Status Change |
Receiver
Line Status1 |
Transmitter Holding
Register Empty1 |
Receiver
Buffer Full |
|||
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
1BASIC/WS and BASIC/UX 700 only
STATUS Register 255 | BASIC/UX 700 Only:
0 = Interface not locked 1 = Interface locked |
CONTROL Register 255 | BASIC/UX 700 Only:
0 = Unlock interface 1 = Lock interface to current process |
NOTE | This section does not apply to HP BASIC/UX 700. |
---|
Unless indicated otherwise, the Status Register returns the current value for a given parameter; the Control Register sets a new value.
See the HP BASIC Interface Reference for changes to RS-232C and Datacomm Registers.
Register | Function |
---|---|
0 | Control: Interface Reset; Status: Interface Card ID |
1 (Status only) | Hardware Interrupt Status: 1=Enabled, 0=Disabled |
2 (Status only) | Datacomm activity: 0=inactive, 1=ENTER in process, 2=OUTPUT in process |
3 | Select Protocol: 1=Async, 2=Data Link1 |
4 (Status only) | Cause of ON INTR program branch |
5 | Control: Terminate transmission; Status: Inbound queue status |
6 | Control: Send BREAK to remote; Status: 1=BREAK pending |
7 (Status only) | Current modem receiver line states |
8 | Modem driver line states |
9 (Status only) | Control block TYPE (supported on BASIC/UX) |
10 (Status only) | Control block MODE (not supported on BASIC/UX) |
11 (Status only) | Available outbound queue space |
12 | Control: Connect/Disconnect line; Status: Line connection status (not supported on BASIC/UX) |
13 | ON INTR mask |
14 | Control Block mask (not supported on BASIC/UX) |
15 | Modem Line interrupt mask |
16 | Connection timeout limit (not supported on BASIC/UX) |
17 | No Activity timeout limit (not supported on BASIC/UX) |
18 | Lost Carrier timeout limit (not supported on BASIC/UX) |
19 | Transmit timeout limit (not supported on BASIC/UX) |
20 | Async: Transmit baud rate (line speed) |
Data Link: Set Transmit/Receive baud rate (line speed) | |
21 | Async: Incoming (receiver) baud rate (line speed) (not supported on BASIC/UX) |
Data Link: GID address (0 thru 26 corresponds to @ thru Z ) | |
22 | Async: Protocol handshake type |
Data Link: DID address (0 thru 26 corresponds to @ thru Z ) | |
23 | Hardware handshake type: ON/OFF, HALF/FULL duplex, Modem/Non-modem |
24 | Async: Control Character mask (not supported on BASIC/UX) |
Data Link: Block Size limit | |
25 (Status only) | Number of received errors since last interface reset (not supported on BASIC/UX) |
26 | Async: First protocol character (ACK/DC1) |
Data Link: NAKs received since last interface reset |
1For BASIC/UX information on this register, see the HP BASIC Interface Reference.
For the BASIC Workstation, registers 27-35, 37, and 39 are used with Async protocol only. They are not accessible during Data Link operations. Note that registers 27-33 and 37-39 are not supported on BASIC/UX and that BASIC/UX does not support Data Link operations.
Register | Function |
---|---|
27 | Second protocol handshake character (ENQ/DC3) |
28 | Number of characters in End-of-line sequence |
29 | First character in EOL sequence |
30 | Second character in EOL sequence |
31 | Number of characters in PROMPT sequence |
32 | First character in PROMPT sequence |
33 | Second character in PROMPT sequence |
34 | Data bits per character excluding start, stop and parity |
35 | Stop bits per character (0=1, 1=1.5, and 2=2 stop bits) |
36 | Parity sense: 0=NONE, 1=ODD, 2=EVEN, 3=ZERO, 4=ONE Data Link: 0=NONE (HP 1000 host), 1=ODD (HP 3000 host) |
37 | Inter-character time gap in character times (Async only) |
38 (Status only) | Transmit queue status (1=empty) |
39 | BREAK time in character times (Async only) |
Control registers accept values in the range of zero through 255. Some registers require specified values, as indicated. Illegal values or values less than zero or greater than 255, cause ERROR 327.
Reset value, shown for various Control Registers, is the default value used by the interface after a reset or power-up until the value is overridden by a CONTROL statement.
Status 0 | Card Identification Value returned: 52 indicates a 98628
(if 180 is returned, check select code switch cluster and make sure switch R is ON); 5 indicates a 98642 (if 133 is returned, check select code switch cluster and make sure switch R is ON). |
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Control 0 | Card Reset Any value, 1 through 255, resets the card. Immediate execution.
Data in queues is destroyed. |
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Status 1 | Hardware Interrupt Status (not used in most applications)
|
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Status 2 | Datacomm Activity
(Non-zero only during multi-line function calls.) |
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Status 3 | Current Protocol Identification: 1 = Async, 2 = Data Link.
|
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Control 3 | Protocol to be used after next card reset (CONTROL Sc,0;1):
1 = Async Protocol, 2 = Data Link Protocol (Data Link BASIC/WS only). This
register overrides default switch configuration.
|
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Status 4 | Cause of ON INTR program branch. |
Bit | Function: Async Protocol | Function: Data Link Protocol |
---|---|---|
0 | Data and/or Control Block available | Data Block Available |
1 | Prompt received | Space available for a new transmission block |
2 | Framing and/or parity error | Receive or transmit error |
3 | Modem line change | Modem line change |
4 | No Activity timeout (forces a disconnect) (BASIC/WS only) | No Activity timeout (forces a disconnect) (BASIC/WS only) |
5 | Lost carrier or connection timeout(forces a disconnect) (BASIC/WS only) | Lost carrier or connection timeout(forces a disconnect) (BASIC/WS only) |
6 | End-of-line received | Not Used |
7 | Break received | Not used |
Contents of this register are cleared when a STATUS statement is executed to it.
Status 5 | Inbound queue status (not supported by BASIC/UX)
|
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Control 5 | Terminate Transmission (not supported by BASIC/UX) OUTPUT S,5;0
is equivalent to OUTPUT S;END
|
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Status 6 | Break status: 1 = BREAK transmission pending, 0 = no BREAK pending. | |||||||||||||||||||||||||||||||||||||||||||||||
Control 6 | Send Break; causes a Break to be sent as follows:
|
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Status 7 | Modem receiver line states (values shown are for male cable connector
option for connection to modems).
|
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Status 8 | Returns modem driver line states. | |||||||||||||||||||||||||||||||||||||||||||||||
Control 8 | Sets modem driver line states (values shown are for male cable connector
option for connection to modems).
|
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Status 9 | Returns control block TYPE if last ENTER terminated on a control block. See Status Register 10 for values (not supported on BASIC/UX). | |||||||||||||||||||||||||||||||||||||||||||||||
Status 10 | Returns control block MODE if last ENTER terminated on a control block
(not supported on BASIC/UX).
1Parity/framing error control blocks are not generated when characters with parity and/or framing errors are replaced by an underscore (_) character.
1This type is used primarily in specialized applications.
|
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Status 11 | Returns available outbound queue space (in bytes), provided there is
sufficient space for at least three control blocks. If not, value is zero.
|
Status 12 | Datacomm Line connection status (not supported on BASIC/UX)
1When using Data Link: Connected - datacomm idle Reset value -- 0 if |R| on interface select code switch cluster is ON (1).
|
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Control 12 | Connects, initiates auto-dial sequence, and disconnects interface from
datacomm line (not supported on BASIC/UX).
|
Status 13 | Returns current ON INTR mask | ||||||||||||||||||||||||||||||||||||||||||||||||
Control 13 | Sets ON INTR mask If a CONTROL statement is used to access this register,
the control block is placed in the outbound queue. If the ENABLE INTR...
statement is used with a mask, the mask value is placed directly in the control
register, bypassing any queue delays.
1If bits 4 and 5 are not set, the corresponding errors can be trapped by using an ON ERROR statement.
1If bits 4 and 5 are not set, the corresponding errors can be trapped by using an ON ERROR statement. Reset value = 0 |
Status 14 | Returns current Control Block mask (not supported on BASIC/UX). |
Control 14 | Sets Control Block mask. Control block information is queued sequentially with incoming data as follows (not supported on BASIC/UX). |
Bit | Value | Async Control Block Passed | Data Link Control Block Passed |
---|---|---|---|
0 | 1 | Prompt position | Transparent/Normal Mode1 |
1 | 2 | End-of-line position | ETX Block Terminator |
2 | 4 | Framing and/or Parity error3 | ETB Block Terminator2 |
3 | 8 | Break received | &empty |
1Transparent/Normal format identification control block occurs at the beginning of a given block of data in the receive queue.
2ETX and ETB Block Termination identification control blocks occur at the END of a given block of data in the receive queue.
3This control block precedes each character containing a parity or framing error.
Reset Value=0 (Control Blocks disabled)
Reset Value=6 (ETX/ETB Enabled) |
|
Bits 4, 5, 6, and 7 are not used. |
Status 15 | Returns current modem line interrupt mask. | ||||||||||||||||||||||||||||||||||||
Control 15 | Sets modem line interrupt mask. Enables an interrupt to ON INTR when
Bit 3
of Control Register 13 is set as follows:
Reset value=0 Note that bit functions are the same as for STATUS register 7. Functions shown are for male connector cable option for modem connections. |
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Status 16 | Returns current connection timeout limit (not supported on BASIC/UX). | ||||||||||||||||||||||||||||||||||||
Control 16 | Sets Attempted Connection timeout limit. Acceptable values: 1 through
255 seconds.
0=timeout disabled (not supported on BASIC/UX) Reset value=25 seconds |
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Status 17 | Returns current No Activity timeout limit (not supported on BASIC/UX). | ||||||||||||||||||||||||||||||||||||
Control 17 | Sets No Activity timeout limit (not supported on BASIC/UX). Acceptable
values:
1 through 255 minutes. 0=timeout disabled. Reset Value=10 minutes (disabled if Async, non-modem handshake). |
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Status 18 | Returns current Lost Carrier timeout limit (not supported on BASIC/UX). | ||||||||||||||||||||||||||||||||||||
Control 18 | Sets Lost Carrier timeout limit in units of 10 ms. Acceptable values:
1 through 255. 0=timeout disabled. Reset Value=40 (400 milliseconds) (not supported on BASIC/UX) |
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Status 19 | Returns current Transmit timeout limit (not supported on BASIC/UX). | ||||||||||||||||||||||||||||||||||||
Control 19 | Sets Transmit timeout limit (loss of clock or CTS not returned by modem
when transmission is attempted)
(not supported on BASIC/UX). Acceptable values: 1 through 255. 0=timeout disabled. Reset Value=10 seconds |
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Status 20 | Returns current transmission speed (baud rate). See table for values.
For BASIC/UX information
on this register, see the HP BASIC Interface Reference. |
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Control 20 | Sets transmission speed (baud rate) as follows:
1Async only. These values cannot be used with Data Link. These values set transmit speed ONLY for Async; transmit AND receive speed for Data Link. Default value is defined by the interface card configuration switches. For BASIC/UX information on this register, see the HP BASIC Interface Reference
|
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Status 21 | Protocol dependent. Returns receive speed (Async) or GID address (Data
Link) as specified by Control Register 21.
For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
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Control 21 | Protocol dependent. Functions are as follows:
(For BASIC/UX information on this register, see the HP BASIC Interface Reference.)
|
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Status 22 | Protocol dependent. Returns DID (Data Link) or protocol handshake type
(Async) as specified by Control Register 22.
For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
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Control 22 | Protocol dependent. Functions are as follows:
(For BASIC/UX information on this register, see the HP BASIC Interface Reference.)
|
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Status 23 | Returns current hardware handshake type (not supported on BASIC/UX). | ||||||||||||||||||||||||||||||||||||
Control 23
|
Sets hardware handshake type as follows:
|
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Status 24
|
Protocol dependent. Returns value set by preceding CONTROL statement to Control Register 24 (not supported on BASIC/UX). |
Control 24
|
Protocol dependent. Functions as follows (not supported on BASIC/UX): | |||||||||||||||||||||||||||||||
Data Link Protocol: | Set outbound block size limit.
Reset outbound block size limit=512 bytes |
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Async Protocol: | Set mask for control characters included in receive data message queue.
|
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Reset value=127 (bits 0 -- 6 set) | ||||||||||||||||||||||||||||||||
Status 25 | Returns number of received errors since power up or reset (not supported on BASIC/UX). |
NOTE |
---|
Control Registers 26 through 35, Status Registers 27 through 35, and Control and Status Registers 37 and 39 are used for ASYNC protocol ONLY. They are not available during Data Link operation. |
Status 26 | Protocol dependent |
Data Link Protocol:
(BASIC/WS only) |
Returns number of transmit errors (NAKs received) since last interface reset. |
Async Protocol: | Returns first protocol handshake character (ACK or DC1). |
Control 26
(Async only) (RMB-UX supports only 17=DC1) |
Sets first protocol handshake character as follows: 6=ACK, 17=DC1. Other values used for special applications only. Reset value=17 (DC1). Use ACK when Control Register 22 is set to 1 or 2. Use DC1 when Control Register 22 is set to 3, 4, or 5. |
Status 27
(Async only) |
Returns second protocol handshake character. |
Control 27
(Async only) (RMB-UX supports only 19=DC3) |
Sets second protocol handshake character as follows: 5=ENQ, 19=DC3. Other values used for special applications only. Reset value=19 (DC3). Use ENQ when Control Register 22 is set to 1 or 2. Use DC3 when Control Register 22 is set to 3, 4, or 5. |
Status 28
(Async only) |
Returns number of characters in inbound End-of-line delimiter sequence. |
Control 28
(Async only) |
Sets number of characters in End-of-line delimiter sequence Acceptable values are 0 (no EOL delimiter), 1, or 2. Reset Value=2 |
Status 29
(Async only) |
Returns first End-of-line character. |
Control 29
(Async only) |
Sets first End-of-line character. Reset Value=13 (carriage return) |
Status 30
(Async only) |
Returns second End-of-line character. |
Control 30
(Async only) |
Sets second End-of-line character. Reset Value=10 (line feed) |
Status 31
(Async only) |
Returns number of characters in Prompt sequence. |
Control 31
(Async only) |
Sets number of characters in Prompt sequence. Acceptable values are 0 (Prompt disabled), 1 or 2. Reset Value=1 |
Status 32
(Async only) |
Returns first character in Prompt sequence. |
Control 32
(Async only) |
Sets first character in Prompt sequence. Reset Value=17 (DC1) |
Status 33
(Async only) |
Returns second character in Prompt sequence. |
Control 33
(Async only) |
Sets second character in Prompt sequence. Reset Value=0 (null) |
Status 34
(Async only) |
Returns the number of bits per character. |
Control 34
(Async only) |
Sets the number of bits per character as follows:
0=5 bits/character 2=7 bits/character 1=6 bits/character 3=8 bits/character) When 8 bits/char, parity must be NONE, ODD, or EVEN. Reset Value is determined by interface card default switches. For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
Status 35
(Async only) |
Returns the number of stop bits per character. |
Control 35
(Async only) |
Sets the number of stop bits per character as follows: 0=1 stop bit 1=1.5 stop bits 2=2 stop bits Reset Value: 2 stop bits if 150 baud or less, otherwise 1 stop bit. Reset Value is determined by interface configuration switch settings. |
Status 36 | Returns current Parity setting. |
Control 36 | Sets Parity for transmitting and receiving as follows: |
Data Link Protocol: | 0=NO Parity; Network host is HP 1000 Computer.
1=ODD Parity; Network host is HP 3000 Computer. Reset Value=0 |
Async Protocol: | 0=NONE; no parity bit is included with any characters.
1=ODD; Parity bit SET if there is an EVEN number of 1 s in the character body. 2=EVEN; Parity bit OFF if there is an ODD number of 1 s in the character body. 3="0"; Parity bit is always ZERO, but parity is not checked (BASIC/WS only). 4="1"; Parity bit is always SET, but parity is not checked (BASIC/WS only). Default is determined by interface configuration switches. If 8 bits per character, parity must be NONE, ODD, or EVEN. For BASIC/UX information on this register, see the HP BASIC Interface Reference. |
Status 37
(Async only) |
Returns inter-character time gap in character times. |
Control 37
(Async only) |
Sets inter-character time gap in character times. Acceptable values: 1 through 255 character times. 0=No gap between characters. Reset Value=0 |
Status 38 | Returns Transmit queue status (not supported on BASIC/UX). If returned value=1, queue is empty, and there are no pending transmissions. |
Status 39
(Async only) |
Returns current Break time (in character times). |
Control 39
(Async only) |
Sets Break time in character times (not supported on BASIC/UX). Acceptable values are: 2 through 255. Reset Value=4. |
NOTE |
---|
This section does not apply to HP BASIC/UX 700. |
STATUS Register 0 | Card Identification. 6 is always returned. |
CONTROL Register 0 | Interface Reset. Any non-zero value causes a reset. |
STATUS Register 1 | Interrupt and DMA Status. |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
Interrupt enabled | Interrupt requested | Interrupt level | Interrupt level | 0 | 0 | DMA1 | DMA0 |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
Bit 7 is set (1) if interrupts are currently enabled.
Bit 6 is set (1) when the card is currently requesting service. (This bit is independent of Interrupt Enabled, bit 7).
Bits 5 and 4 constitute the card's hardware interrupt level:
Bit 5 | Bit 4 | Hardware Interrupt\Level |
---|---|---|
0 | 0 | 3 |
0 | 1 | 4 |
1 | 0 | 5 |
1 | 1 | 6 |
Bits 3 and 2 are not used (always 0).
Bit 1 is set (1) if DMA channel one is currently enabled.
Bit 0 is set (1) if DMA channel is currently enabled.
On POR (Power on Reset), interrupts are disabled (Bit 7=0) and both DMA channels are disabled. The interrupt level reflects the hardware state and is always the same.
STATUS Register 10 | Peripheral Status. |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | nError | Select | PError |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
Bits 7-3 | Not used (always 0). |
Bit 2 (nError) | If this bit is set (1), nError is asserted low. |
Bit 1 (Select) | If this bit is set (1), Select is asserted high. |
Bit 0 (PError) | If this bit is set (1), PError is asserted high. |
These bus lines are controlled by the peripheral. This register merely reflects the state of these bus lines, and therefore does not have a default POR setting.
STATUS Register 11 | Communication Status |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | FIFO Full | FIFO Empty | nStrobe | Busy | nAck |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
Bits 7-5 | Not used (always 0). |
Bit 4 (FIFO Full) | If this bit is set (1), the hardware FIFO is full. |
Bit 3 (FIFO Empty) | If this bit is set (1), the hardware FIFO is empty. |
Bit 2 (nStrobe) | If this bit is set (1), nAck is asserted low. |
Bit 1 (Busy) | If this bit is set (1), Busy is asserted high. |
Bit 0 (nAck) | If this bit is set (1), nAck is asserted low. |
On POR the hardware FIFO (first in/first out register) is empty, the nStrobe line should not be asserted, and the remaining lines are controlled by the peripheral. This register reflects the state of the peripheral owned lines, and therefore these register bits do not have a default POR setting.
STATUS Register 12 | Host Line Control |
CONTROL Register 12 | Host Line Control |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | nInit | nSelectIn | Wr/nRd |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
Bits 7-3 | Not used (always 0). |
Bit 2 (nInit) | If this bit is set (1), nInit is asserted low. |
Bit 1 (nSelectIn) | If this bit is set (1), nSelectIn is asserted low. |
Bit 0 (Wr/nRd) | If this bit is set (1), Wr/nRd is asserted high. |
On POR, nInit is asserted low, nSelectIn is released high, and Wr/nRd is released high.
STATUS Register 13 | I/O Control. |
CONTROL Register 13 | I/O Control. |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | 0 | I/O Modifier | Input/ nOutput |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
Bits 7-2 | Not used (always 0) |
Bit 1 (I/O Modifier) | If cleared, outbound transfers handshake with both BUSY and nAck and inbound transfers will use the FIFO. If set, outbound transfers will handshake with BUSY only and inbound transfers will only use one location in the FIFO (FIFO disabled). |
Bit 0 (Input/nOutput) | If this bit is set to 1, Input is selected. If this bit is reset (0), output is selected. |
On POR bits 1 and 0 are reset to 0.
STATUS Register 14 | FIFO |
CONTROL Register 14 | FIFO |
In order to get valid information when reading the hardware FIFO, the I/O direction must be "input" and the FIFO must not be empty (see the Hardware I/O Status and Control register and the Communication Status register). If either of these conditions are not true, reading this register will not cause an error, but unpredictable results may occur.
For writing, the same rules apply. The I/O direction must be "output" and the FIFO must not be full. If either of these conditions are not true, writing this register will not cause an error, but the data written will not be entered into the hardware FIFO.
NOTE |
---|
This register should not be used unless the program has full control of this select code. For example, if this register is being used while the driver is attempting a transfer, it is very likely the transfer will fail. |
STATUS Register 20 | Peripheral Type |
Decimal\value | Peripheral type |
---|---|
0 | No device attached. |
1 | Output-only device is currently attached. |
2 | An HP bidirectional device is attached. |
10 | User-specified no device. |
11 | User-specified output only device. |
12 | User-specified HP bidirectional device. |
CONTROL Register 20 | Peripheral Type |
Decimal\value | Peripheral type |
---|---|
0 | No device attached. |
10 | User-specified no device. |
11 | User-specified output only device. |
12 | User-specified HP bidirectional device. |
I/O initialize resets peripheral.
CONTROL Register 22 | Peripheral Reset |
Writing any non-zero value to this register causes the driver to attempt a hardware soft reset on the attached peripheral. The driver will assert the nInit line, wait, release the nInit line, and wait for Busy to be released.
STATUS Register 23 | Interrupt State |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
FIFO Full | FIFO Empty | 0 | Busy | nAck | nError | Select | PError |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
This register returns the interrupt requests that are currently being made by the driver.
Bit 7 (FIFO Full) | If this bit is set (1), an interrupt will be requested when the hardware FIFO transitions to full. |
Bit 6 (FIFO Empty) | If this bit is set (1), an interrupt will be requested when the hardware FIFO transitions to empty. |
Bit 5 (Busy) | Not used (always 0). |
Bit 4 (Busy) | If this bit is set (1), an interrupt will be requested when the Busy signal is low. |
Bit 3 (nAck) | If this bit is set (1), an interrupt will be requested when the nAck signal transitions low. |
Bit 2 (nError) | If this bit is set (1), an interrupt will be requested when the nError signal transitions. |
Bit 1 (Select) | If this bit is set (1), an interrupt will be requested when the Select signal transitions. |
Bit 0 (PError) | If this bit is set (1), an interrupt will be requested when the PError signal transitions. |
On POR the driver disables all interrupt conditions, thus this register will return a 0 on POR.
STATUS Register 24 | Driver Options |
CONTROL Register 24 | Driver Options |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | Ignore PError | Write Verify | Wr/nRd low | Use nAck |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
Bits 7-4 | Not used (always 0). |
Bit 3 (Ignore PError) | If this bit is set to 1, the interface will communicate with the device
despite PError assertion.
If this bit is set to 0 (the default), an error occurs on a communication attempt with PError asserted. |
Bit 2 (Write Verify) | If this bit is set to 1, the interface verifies that the peripheral receives
data on each byte sent.
If this bit is set to 0 (the default), verification does not occur. |
Bit 1 (Wr/nRd low) | If this bit is set to 1, Wr/nRd is always LOW. If this bit is set to 0 (the default), Wr/nRd HIGH on output, LOW on input. |
Bit 0 (Use nAck) | If this bit is set to 1, the interface uses nAck to complete the output handshake. If this bit is set to 0 (the default), the interface uses Busy to complete the output handshake. |
STATUS Register 26 | Driver State |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Disable by user | Inactive ERROR | Write | Read | 0 | 0 | 0 | Active Xfer |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
The driver states are:
DISABLED_BY_USER | =80h (hexadecimal) |
INACTIVE_ERROR | =40h |
INACTIVE_WRITE | =20h |
ACTIVE_WRITE | =21h |
INACTIVE_READ | =10h |
ACTIVE_READ | =11h |
If the POR state of the peripheral type is not "user specified no device" (see register 20) then the POR state for this register is INACTIVE_ERROR. Otherwise, the POR state is DISABLED_BY_USER.
NOTE |
---|
This section does not apply to HP BASIC/UX 700. |
STATUS Register 0 | Card Identification. Always 3. |
CONTROL Register 0 | Interface Reset. Any non-zero value causes a reset. |
STATUS Register 1 | Interrupt and DMA Status |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Interrupts Are Enabled | An Interrupt Is Currently Requested | Interrupt Level Switches (HardwarePriority) | Burst- Mode DMA | Word- Mode DMA | DMA Chan 1 Enabled | DMA Chan 0 Enabled | |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
CONTROL Register 1 | Set PCTL Line. Any non-zero value sets the line. |
STATUS Register 2 | Peripheral Control |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | Handshake In Process | Interrupts Are Enabled | Transfer In Progress |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
CONTROL Register 2 | Peripheral Control |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Not used |
PSTS Error
1Report 0Ignore |
Set CTL1
1Low 0High |
Set CTL0
1Low 0High |
||||
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 3 | Data In (16 bits) |
CONTROL Register 3 | Data Out (16 bits) |
STATUS Register 4 | Interface Ready. Interface is Ready for a subsequent data transfer: 1=Ready, 0=Busy. |
STATUS Register 5 | Peripheral Status |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | PSTS Ok | EIR Line Low | STI1 Line Low | STI0 Line Low |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
Interrupt Enable Register | (ENABLE INTR) |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Not used | Not used | Not used | Not used | Not used | Not used | Enable Interface Ready Interrupt | Enable EIR Interrupt |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 255 |
*BASIC/WS and BASIC/DOS accept this command but always return the value "3".
|
||||||
CONTROL Register 255 |
*BASIC/WS and BASIC/DOS accept this command but always set the value to "3".
|
NOTE |
---|
This section does not apply to HP BASIC/UX 300/400/700. |
STATUS Register 0 | Card Identification = 4. |
CONTROL Register 0 | Reset Interface (if non-zero value sent). |
STATUS Register 1 | Interrupt Status |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Interrupts are enabled | Interrupt Request | Hardware Interrupt Level Switches | 0 | 0 | 0 | 0 | |
value=128 | value=64 | value=32 | value=16 | value=0 | value=0 | value=0 | value=0 |
CONTROL Register 1 | Reset driver pointer (if non-zero value sent). |
STATUS Register 2 | Busy Bit |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | Hand- shake in progress | Interrupts Enabled | 0 |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
Bit 0 is 1 when a handshake is currently in progress.
CONTROL Register 2 | Request data by Setting CTLA and CTLB (if a non-zero value is sent); this operation also clears an Interrupt Request (clears bit 6 of Status Register 1). |
STATUS Register 3 | Binary Mode: 1 if the interface is currently operating in Binary mode,
and 0 if in BCD mode.
|
CONTROL Register 3 | Set Binary Mode: set Binary Mode if non-zero value sent, and BCD Mode
if zero sent.
|
STATUS Register 4 | Switch and Line States |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
OF Switch Is ON | DATA Switch Is ON | SGN1 Switch Is ON | SGN2 Switch Is ON | OVLD Switch Is ON | SGN1 Input Is True | SGN2 Input Is True | OVLD Input Is True |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
CONTROL Register 4 | Data Out Lines |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
Set DO-7 True | Set DO-6 True | Set DO-5 True | Set DO-4 True | Set DO-3 True | Set DO-2 True | Set DO-1 True | Set DO-0 True |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 5 | BCD Digits DI1 and DI2 |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
DI1-8 is True | DI1-4 is True | DI1-2 is True | DI1-1 is True | DI2-8 is True | DI2-4 is True | DI2-2 is True | DI2-1 is True |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 6 | BCD Digits DI3 and DI4 |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
DI3-8 is True | DI3-4 is True | DI3-2 is True | DI3-1 is True | DI4-8 is True | DI4-4 is True | DI4-2 is True | DI4-1 is True |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 7 | BCD Digits DI5 and DI6 |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
DI5-8 is True | DI5-4 is True | DI5-2 is True | DI5-1 is True | DI6-8 is True | DI6-4 is True | DI6-2 is True | DI6-1 is True |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 8 | BCD Digits DI7 and DI8 |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
DI7-8 is True | DI7-4 is True | DI7-2 is True | DI7-1 is True | DI8-8 is True | DI8-4 is True | DI8-2 is True | DI8-1 is True |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
STATUS Register 9 | BCD Digits DI9 and DI10 |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
DI9-8 is True | DI9-4 is True | DI9-2 is True | DI9-1 is True | DI10-8 is True | DI10-4 is True | DI10-2 is True | DI10-1 is True |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
NOTE |
---|
This section does not apply to HP BASIC/UX 300/400/700. |
STATUS Register 0 | ID Register. This register contains a value of 27 (decimal) which is the ID of an EPROM Programmer card. |
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
value=128 | value=64 | value=32 | value=16 | value=8 | value=4 | value=2 | value=1 |
CONTROL Register 0 | Interface Reset. Writing any non-zero value into this register resets the card; writing a value of zero causes no action. |
STATUS Register 1 | Read Program Time. A value of 0 indicates that the program time is 52.5 milliseconds for each 16-bit word (default); a non-zero value indicates that the program time is 13.1 milliseconds. |
CONTROL Register 1 | Set Program Time. Writing a value of 0 into this register sets the program time to 52.5 milliseconds for each 16-bit word; any non-zero value sets program time to 13.1 milliseconds. |
STATUS Register 2 | Read Target Address. This register contains the offset address (relative to the card's base address) at which the next word of data will be read (via STATUS Register 3) or written (via CONTROL Register 3). The default address is 0, which is the address of the first byte on the card. |
CONTROL Register 2 | Set Target Address. Writing to this register sets the offset address at which the next word of data will be read (via STATUS Register 3) or written (via CONTROL Register 3). The target address must always be an even number. |
STATUS Register 3 | Read Word at Target Address. This register contains the 16-bit word at the current target address. |
CONTROL Register 3 | Write Word at Target Address. Writing a data word to this register programs a 16-bit word at the current target address. The target address must be set (via CONTROL register 2) before every word is written. Automatic verification is also performed after the word is programmed. |
STATUS Register 4 | Current Memory Card Capacity (in bytes). This register contains the current capacity of a fully loaded card in bytes; it also indirectly indicates which type of EPROM devices are being used on the card. If 262 144 is returned, then 27128 EPROMs are being used; if 131 072 is returned, then 2764 devices are being used. A 0 is returned if the programmer card is not currently connected to any EPROM memory card. |
CONTROL Register 4 | Undefined. |
STATUS Register 5 | Number of Contiguous, Erased Bytes. Reading this register causes the system to begin counting the number of subsequent bytes, beginning at the current target address, that are erased (or are empty sockets). The counting is stopped when a programmed byte (i.e., one containing at least one logical 0) is found or when the end of the card is reached. If the byte at the current target address is not FF, then a count of 0 is returned. Error 84 is reported if the programmer card is not currently connected to any EPROM card. |
CONTROL Register 5 | Undefined. |
STATUS Register 6 | Base Address of EPROM Memory Card. This register contains the (absolute) base address of the EPROM memory card to which the programmer card is currently connected; this base address is also the absolute address of the first word on the card. Error 84 is reported if the programmer card is not currently connected to any EPROM memory card. |
CONTROL Register 6 | Undefined. |
NOTE |
---|
This section does not apply to HP BASIC/UX 700. |
BASIC/UX supports SRM STATUS Registers 3 and 6. All other registers either cause an error or return a value, depending on the current ERRORMODE setting (specified on the rmb command line or in the configuration file). If ERRORMODE is off, then STATUS Register 0 returns 52, and all other registers return 0.
STATUS Register 0 | Card Identification 52 if the Remote Control switch (R) is set to 0 (closed); 180 if switch is set to 1 (open). | ||||||||
STATUS Register 1 | Interface Interrupts 1=interrupts enabled; 0=interrupts disabled. | ||||||||
STATUS Register 2 | Interface Busy 1=busy; 0=not busy. | ||||||||
STATUS Register 3 | Interface Firmware ID Always 3 (the firmware ID of the SRM interface). | ||||||||
STATUS Register 4 | Not Implemented | ||||||||
STATUS Register 5 | Data Availability
|
||||||||
STATUS Register 6 | Node Address of SRM Interface Node address of the SRM interface installed in this computer which is set to the specified select code. The range of node addresses is 0 through 63. | ||||||||
STATUS Register 7 | CRC Errors Total number of cyclic redundancy check (CRC) errors detected by the interface since powerup or [Reset] ([RESET]). | ||||||||
STATUS Register 8 | Number of Buffer Overflows Total number of times the receive buffer has overflowed since powerup or [Reset] ([RESET]). | ||||||||
STATUS Register 11 | Available space Amount of available space (number of bytes) in the transmit-data buffer. | ||||||||
STATUS Register 12 | Number of Retries Number of transmission retries performed since powerup or [Reset] ([RESET]). |
STATUS Register 0 | Parity Checking for Memory Is Currently Enabled/Disabled
0 = currently disabled; 1 = currently enabled |
CONTROL Register 0 | Enable/Disable Parity Checking for Memory (not supported on BASIC/UX
or BASIC/DOS)
0 = disable; 1 = enable |
STATUS Register 1 | External (16 Kbyte) Cache Is Currently Enabled/Disabled
0 = currently disabled; 1 = currently enabled |
CONTROL Register 1 | Enable/Disable External (16 Kbyte) Cache (not supported on BASIC/UX or
BASIC/DOS)
0 = disable; 1 = enable |
STATUS Register 2 | Floating-Point Math Hardware Is Currently Enabled/Disabled (HP 98635
Card, MC68881, or MC68882 Co-Processor) (not supported on BASIC/UX 700)
0 = currently disabled; 1 = currently enabled |
CONTROL Register 2 | Enable/Disable Floating-Point Math (HP 98635 Card, MC68881 or MC68882
Co-Processor) (not supported on BASIC/UX 700)
0 = disable; 1 = enable |
STATUS Register 3 | MC68020 (256 Byte), MC68030, or MC68040 Cache Is Currently Enabled/Disabled
0 = currently disabled; 1 = currently enabled |
CONTROL Register 3 | Enable/Disable MC68020 (256 Byte), MC68030, or MC68040 Cache (not supported
on BASIC/UX)
0 = disable; non-0 = enable |
NOTE |
---|
With computers that have a MC68030 or MC68040 processor, enabling or disabling this internal cache also enables/disables the external cache (since they are not independent). To determine which processor you have, use SYSTEM$("SYSTEM ID"). A result of S300:20 indicates you have a 68020, S300:30 indicates a 68030 processor, and S300:40 indicates a 68040 processor. |
STATUS Register 4 | Battery-Backed Clock Type
|
||||||||
STATUS Register 5 | Background Process and Redirection
|
||||||||
STATUS Register 6 | MC68040 cache is in copyback/writethrough mode. (Not supported on BASIC/UX
700)
0 = writethrough; 1 = copyback |
||||||||
CONTROL Register 6 | Set MC68040 cache to copyback/writethrough mode. (Not supported on BASIC/UX
700)
0 = writethrough; 1 = copyback |
||||||||
STATUS Register 7 | Math Exception Register Returns math exceptions control flag values. See CONTROL Register 7 for definitions. | ||||||||
CONTROL Register 7 | Math Exception Register
Sets math exceptions control flag values.
1Generates a math exception (error 21) on underflow. 2Enables hardware's fastmode, if available, causing the hardware to substitute 0.0 for underflowed values. If the hardware does not support fastmode, then this field is set to error mode. 3Causes all underflows to be ignored. This can result in denormalized numbers in the range 2.2E-308 to 4.5E-324. For values below 4.5E-324 the result is 0.0. |
NOTE |
---|
This section applies to HP BASIC/UX only. |
STATUS Register 1 | Status of EXT Signal 1 blist width=1.78in>
|
||||||
STATUS Register 2 | Status of EXT Signal 2
|
||||||
STATUS Register 32 | Status of EXT Signal 32 |
SRM/UX status register have been implemented to correspond as closely as possible with the SRM interface card status registers, except that there are additional registers for which there is no SRM analog. In addition, new LAN control register have been implemented.
STATUS Register 0 | Card Identification
|
||||||||||||
STATUS Register 1 | Interface Interrupts
|
||||||||||||
STATUS Register 2 | Not implemented (interface busy on SRM) | ||||||||||||
STATUS Register 3 | Not implemented (interface Firmware ID on SRM) | ||||||||||||
STATUS Register 5 | Data Availability
This will always be the result, because the LAN card's performance is so high. The HP BASIC user will never perceive any other situation.
|
||||||||||||
STATUS Register 6 | Node Address
If the SRM binary is not loaded, STATUS Register 6 returns 0. If the SRM binary is loaded, a pseudo node number is provided by the SRM/UX server (from /etc/srmdconf). This 2-digit number is used for a node-specific autostart file, such as /SYSTEMS/AUTOSTxx.
|
||||||||||||
STATUS Register 7 | CRC Errors (and Frame Errors)
Cyclic redundancy check errors plus frame error detected since powerup or reset. |
||||||||||||
STATUS Register 8 | Number of Buffer Overflows
Returns number of overflows in receive buffers since powerup or reset. |
||||||||||||
STATUS Register 9 | Card State
|
||||||||||||
STATUS Register 11 | Amount of available Space in Transmit Buffer | ||||||||||||
STATUS Register 12 | Number of Transmission Retries since powerup of reset | ||||||||||||
STATUS Register 13 | Current scale factor for connection establishment timeouts.
Default value is 1. Default is reset at powerup and SCRATCH A. The legal range of values is 1 through 32. |
||||||||||||
STATUS Register 14 | Current scale factor for normal operations timeouts.
Default value is 1. Default is reset at powerup and SCRATCH A. legal range of values is 1 through 32. |
||||||||||||
STATUS Register 21-26 | Link Level Address - 6 Bytes
Status registers 21 through 26 each contain one byte of the Link Level Address. The first byte is in register 21, the second byte is in register 22, and so on through register 26. |
||||||||||||
CONTROL Register 18 | Initialize driver statistics to 0
Ordinarily done at power up. |
||||||||||||
CONTROL Register 35 | Set Default Configuration
Causes driver to set all of its pseudo registers to power up default values; hardware is not reconfigured.
|