Setting log file to '/home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file '/usr/local/diamond/3.12/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file '/home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_tx.v'
(VERI-1482) Analyzing Verilog file '/home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v'
WARNING - /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(101,11-101,24) (VERI-2170) data object 'uart_rx_state' is already declared
INFO - /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(88,11-88,24) (VERI-1967) previous declaration of 'uart_rx_state' is from here
WARNING - /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(101,11-101,24) (VERI-1329) second declaration of 'uart_rx_state' ignored
(VERI-1482) Analyzing Verilog file '/home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v'
INFO - /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(3,8-3,16) (VERI-1018) compiling module 'nvm_ctrl'
INFO - /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(3,1-639,10) (VERI-9000) elaborating module 'nvm_ctrl'
INFO - /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_tx.v(2,1-51,10) (VERI-9000) elaborating module 'uart_tx_uniq_1'
INFO - /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v(4,1-111,10) (VERI-9000) elaborating module 'uart_rx_uniq_1'
Done: design load finished with (0) errors, and (2) warnings