Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Sun May 8 22:04:04 2022 Command Line: synthesis -f nvm_ctrl_nvm_ctrl_lattice.synproj -gui -msgset /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 5. The -t option is TQFP100. The -d option is LCMXO2-1200HC. Using package TQFP100. Using performance grade 5. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200HC ### Package : TQFP100 ### Speed : 5 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced The -top option is not used. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /home/jarin/storage/main/backup_mg/works/nvm/fpga/2 (searchpath added) -p /usr/local/diamond/3.12/ispfpga/xo2c00/data (searchpath added) -p /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl (searchpath added) -p /home/jarin/storage/main/backup_mg/works/nvm/fpga/2 (searchpath added) Verilog design file = /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_tx.v Verilog design file = /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v Verilog design file = /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v NGD file = nvm_ctrl_nvm_ctrl.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] WARNING - synthesis: Setting nvm_ctrl as the top-level module. To specify the top-level module explicitly, use the -top option. Technology check ok... Analyzing Verilog file /usr/local/diamond/3.12/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_tx.v. VERI-1482 Analyzing Verilog file /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v. VERI-1482 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(101): uart_rx_state is already declared. VERI-1116 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(101): second declaration of uart_rx_state ignored. VERI-1329 INFO - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(88): uart_rx_state is declared here. VERI-1310 Analyzing Verilog file /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v. VERI-1482 Analyzing Verilog file /usr/local/diamond/3.12/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): nvm_ctrl INFO - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(3): compiling module nvm_ctrl. VERI-1018 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(193): expression size 32 truncated to fit in target size 3. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(243): expression size 32 truncated to fit in target size 8. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(248): expression size 32 truncated to fit in target size 16. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(254): expression size 32 truncated to fit in target size 16. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(270): expression size 32 truncated to fit in target size 21. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(271): expression size 32 truncated to fit in target size 6. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(288): expression size 32 truncated to fit in target size 6. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(331): expression size 32 truncated to fit in target size 7. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(334): expression size 21 truncated to fit in target size 16. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(335): expression size 21 truncated to fit in target size 16. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(441): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(444): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(460): expression size 32 truncated to fit in target size 21. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(466): expression size 32 truncated to fit in target size 21. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(476): expression size 32 truncated to fit in target size 21. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(478): expression size 32 truncated to fit in target size 11. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(606): expression size 32 truncated to fit in target size 4. VERI-1209 INFO - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_tx.v(2): compiling module uart_tx. VERI-1018 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_tx.v(35): expression size 32 truncated to fit in target size 3. VERI-1209 INFO - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v(4): compiling module uart_rx. VERI-1018 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v(35): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v(53): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v(56): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v(72): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v(84): expression size 32 truncated to fit in target size 5. VERI-1209 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/uart_rx.v(87): expression size 32 truncated to fit in target size 5. VERI-1209 Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.42. Top-level module name = nvm_ctrl. WARNING - synthesis: I/O Port JA_DOUT 's net has no driver and is unused. WARNING - synthesis: I/O Port JA_COMP 's net has no driver and is unused. WARNING - synthesis: I/O Port JA_C1 's net has no driver and is unused. WARNING - synthesis: I/O Port JA_C2 's net has no driver and is unused. WARNING - synthesis: I/O Port JA_C3 's net has no driver and is unused. ######## Missing driver on net JA_C1. Patching with GND. ######## Missing driver on net JA_C2. Patching with GND. ######## Missing driver on net JA_C3. Patching with GND. WARNING - synthesis: Bit 0 of Register cnt_ic_set is stuck at Zero WARNING - synthesis: Bit 1 of Register cnt_ic_set is stuck at Zero WARNING - synthesis: Bit 2 of Register cnt_ic_set is stuck at Zero WARNING - synthesis: Bit 3 of Register cnt_ic_set is stuck at Zero WARNING - synthesis: Bit 4 of Register cnt_ic_set is stuck at Zero WARNING - synthesis: Bit 10 of Register cnt_ic_set is stuck at Zero WARNING - synthesis: Bit 0 of Register uart_frame_r is stuck at Zero WARNING - synthesis: Bit 1 of Register uart_frame_r is stuck at Zero WARNING - synthesis: I/O Port JA_DOUT 's net has no driver and is unused. WARNING - synthesis: I/O Port JA_COMP 's net has no driver and is unused. WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(259): Register dac_word_i0 is stuck at Zero. VDB-5013 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(614): Register uart_frame_state_i2 is stuck at Zero. VDB-5013 WARNING - synthesis: /home/jarin/storage/main/backup_mg/works/nvm/fpga/2/nvm_ctrl.v(497): Register main_state_i4 is stuck at Zero. VDB-5013 GSR will not be inferred because no asynchronous signal was found in the netlist. Applying 200.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in nvm_ctrl_drc.log. Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... WARNING - synthesis: logical net 'JA_DOUT' has no load. WARNING - synthesis: input pad net 'JA_DOUT' has no legal load. WARNING - synthesis: logical net 'JA_COMP' has no load. WARNING - synthesis: input pad net 'JA_COMP' has no legal load. WARNING - synthesis: DRC complete with 4 warnings. All blocks are expanded and NGD expansion is successful. Writing NGD file nvm_ctrl_nvm_ctrl.ngd. ################### Begin Area Report (nvm_ctrl)###################### Number of register bits => 421 of 1520 (27 % ) CCU2D => 88 FD1P3AX => 213 FD1P3IX => 158 FD1P3JX => 5 FD1S3AX => 11 FD1S3IX => 34 GSR => 1 IB => 6 L6MUX21 => 1 LUT4 => 333 OB => 38 PFUMX => 11 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 3 Net : CLK_32M_c, loads : 311 Net : uart_tx_bit_clock, loads : 73 Net : uart_rx_bit_clock, loads : 39 Clock Enable Nets Number of Clock Enables: 61 Top 10 highest fanout Clock Enables: Net : CLK_32M_c_enable_265, loads : 66 Net : uart_tx_bit_clock_enable_66, loads : 50 Net : CLK_32M_c_enable_93, loads : 33 Net : CLK_32M_c_enable_50, loads : 21 Net : CLK_32M_c_enable_264, loads : 17 Net : CLK_32M_c_enable_256, loads : 17 Net : CLK_32M_c_enable_241, loads : 16 Net : CLK_32M_c_enable_25, loads : 14 Net : CLK_32M_c_enable_229, loads : 13 Net : CLK_32M_c_enable_54, loads : 11 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : CLK_32M_c_enable_265, loads : 66 Net : uart_tx_bit_clock_enable_66, loads : 50 Net : startup_cnt_32__N_436, loads : 33 Net : CLK_32M_c_enable_93, loads : 33 Net : CLK_32M_c_enable_55, loads : 22 Net : uart_frame_cnt_0, loads : 21 Net : CLK_32M_c_enable_50, loads : 21 Net : n4387, loads : 21 Net : n3921, loads : 21 Net : uart_frame_cnt_2, loads : 20 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk2 [get_nets uart_tx_bit_clock] | 200.000 MHz| 151.263 MHz| 4 * | | | create_clock -period 5.000000 -name | | | clk1 [get_nets CLK_32M_c] | 200.000 MHz| 63.824 MHz| 11 * | | | create_clock -period 5.000000 -name | | | clk0 [get_nets uart_rx_bit_clock] | 200.000 MHz| 114.129 MHz| 5 * | | | -------------------------------------------------------------------------------- 3 constraints not met. Peak Memory Usage: 186.320 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 1.429 secs --------------------------------------------------------------