; ===============================================													
; ADuC7023 HEADER FILE REV 1.3													
; ===============================================													
Z_BASE                         EQU       0xFFFF0000
F_BASE                         EQU       0xFFFFF000
MMR_BASE                       EQU       0xFFFF0000
MMR_BASE_LOW                   EQU       0xFFFF0000
MMR_BASE_HIGH                  EQU       0xFFFFF000

; Set ALLOW_DEPRECATED_NAMES true to enable deprecated register names
	GBLL ALLOW_DEPRECATED_NAMES        
ALLOW_DEPRECATED_NAMES         SETL {FALSE}
IRQBASE                        EQU       0xFFFF0000
IRQSTA                         EQU       0xFFFF0000
IRQSIG                         EQU       0xFFFF0004
IRQEN                          EQU       0xFFFF0008
IRQCLR                         EQU       0xFFFF000C
SWICFG                         EQU       0xFFFF0010
IRQBASE                        EQU       0xFFFF0014
IRQVEC                         EQU       0xFFFF001C
IRQP0                          EQU       0xFFFF0020
IRQP1                          EQU       0xFFFF0024
IRQP2                          EQU       0xFFFF0028
IRQP3                          EQU       0xFFFF002C
IRQCONN                        EQU       0xFFFF0030
IRQCONE                        EQU       0xFFFF0034
IRQCLRE                        EQU       0xFFFF0038
IRQSTAN                        EQU       0xFFFF003C
FIQSTA                         EQU       0xFFFF0100
FIQSIG                         EQU       0xFFFF0104
FIQEN                          EQU       0xFFFF0108
FIQCLR                         EQU       0xFFFF010C
FIQVEC                         EQU       0xFFFF011C
FIQSTAN                        EQU       0xFFFF013C
Z_IRQSTA                       EQU       IRQSTA    -Z_BASE
Z_IRQSIG                       EQU       IRQSIG    -Z_BASE
Z_IRQEN                        EQU       IRQEN     -Z_BASE
Z_IRQCLR                       EQU       IRQCLR    -Z_BASE
Z_SWICFG                       EQU       SWICFG    -Z_BASE
Z_IRQBASE                      EQU       IRQBASE   -Z_BASE
Z_IRQVEC                       EQU       IRQVEC    -Z_BASE
Z_IRQP0                        EQU       IRQP0     -Z_BASE
Z_IRQP1                        EQU       IRQP1     -Z_BASE
Z_IRQP2                        EQU       IRQP2     -Z_BASE
Z_IRQP3                        EQU       IRQP3     -Z_BASE
Z_IRQCONN                      EQU       IRQCONN   -Z_BASE
Z_IRQCONE                      EQU       IRQCONE   -Z_BASE
Z_IRQCLRE                      EQU       IRQCLRE   -Z_BASE
Z_IRQSTAN                      EQU       IRQSTAN   -Z_BASE
Z_FIQSTA                       EQU       FIQSTA    -Z_BASE
Z_FIQSIG                       EQU       FIQSIG    -Z_BASE
Z_FIQEN                        EQU       FIQEN     -Z_BASE
Z_FIQCLR                       EQU       FIQCLR    -Z_BASE
Z_FIQVEC                       EQU       FIQVEC    -Z_BASE
Z_FIQSTAN                      EQU       FIQSTAN   -Z_BASE

T_IRQSTA                       EQU       IRQSTA    -IRQBASE   
T_IRQSIG                       EQU       IRQSIG    -IRQBASE   
T_IRQEN                        EQU       IRQEN     -IRQBASE   
T_IRQCLR                       EQU       IRQCLR    -IRQBASE   
T_SWICFG                       EQU       SWICFG    -IRQBASE   
T_IRQBASE                      EQU       IRQBASE   -INTBASE   
T_IRQVEC                       EQU       IRQVEC    -INTBASE   
T_IRQP0                        EQU       IRQP0     -INTBASE   
T_IRQP1                        EQU       IRQP1     -INTBASE   
T_IRQP2                        EQU       IRQP2     -INTBASE   
T_IRQP3                        EQU       IRQP3     -INTBASE   
T_IRQCONN                      EQU       IRQCONN   -INTBASE   
T_IRQCONE                      EQU       IRQCONE   -INTBASE   
T_IRQCLRE                      EQU       IRQCLRE   -INTBASE   
T_IRQSTAN                      EQU       IRQSTAN   -INTBASE   
T_FIQSTA                       EQU       FIQSTA    -IRQBASE   
T_FIQSIG                       EQU       FIQSIG    -IRQBASE   
T_FIQEN                        EQU       FIQEN     -IRQBASE   
T_FIQCLR                       EQU       FIQCLR    -IRQBASE   
T_FIQVEC                       EQU       FIQVEC    -INTBASE   
T_FIQSTAN                      EQU       FIQSTAN   -INTBASE   

IRQSTA_OFFSET                  EQU       0x0000
IRQSIG_OFFSET                  EQU       0x0004
IRQEN_OFFSET                   EQU       0x0008
IRQCLR_OFFSET                  EQU       0x000C
SWICFG_OFFSET                  EQU       0x0010
IRQBASE_OFFSET                 EQU       0x0014
IRQVEC_OFFSET                  EQU       0x001C
IRQP0_OFFSET                   EQU       0x0020
IRQP1_OFFSET                   EQU       0x0024
IRQP2_OFFSET                   EQU       0x0028
IRQP3_OFFSET                   EQU       0x002C
IRQCONN_OFFSET                 EQU       0x0030
IRQCONE_OFFSET                 EQU       0x0034
IRQCLRE_OFFSET                 EQU       0x0038
IRQSTAN_OFFSET                 EQU       0x003C
FIQSTA_OFFSET                  EQU       0x0100
FIQSIG_OFFSET                  EQU       0x0104
FIQEN_OFFSET                   EQU       0x0108
FIQCLR_OFFSET                  EQU       0x010C
FIQVEC_OFFSET                  EQU       0x011C
FIQSTAN_OFFSET                 EQU       0x013C

; REMAP AND SYSTEM CONTROL

REMAPBASE                      EQU       0xFFFF0200
REMAP                          EQU       0xFFFF0220
RSTSTA                         EQU       0xFFFF0230
RSTCLR                         EQU       0xFFFF0234
Z_REMAP                        EQU       REMAP     -Z_BASE
Z_RSTSTA                       EQU       RSTSTA    -Z_BASE
Z_RSTCLR                       EQU       RSTCLR    -Z_BASE

T_REMAP                        EQU       REMAP     -REMAPBASE 
T_RSTSTA                       EQU       RSTSTA    -REMAPBASE 
T_RSTCLR                       EQU       RSTCLR    -REMAPBASE 

REMAP_OFFSET                   EQU       0x0220
RSTSTA_OFFSET                  EQU       0x0230
RSTCLR_OFFSET                  EQU       0x0234

; TIMER 0

T0BASE                         EQU       0xFFFF0300
T0LD                           EQU       0xFFFF0300
T0VAL                          EQU       0xFFFF0304
T0CON                          EQU       0xFFFF0308
T0CLRI                         EQU       0xFFFF030C
Z_T0LD                         EQU       T0LD      -Z_BASE
Z_T0VAL                        EQU       T0VAL     -Z_BASE
Z_T0CON                        EQU       T0CON     -Z_BASE
Z_T0CLRI                       EQU       T0CLRI    -Z_BASE

T_T0LD                         EQU       T0LD      -T0BASE    
T_T0VAL                        EQU       T0VAL     -T0BASE    
T_T0CON                        EQU       T0CON     -T0BASE    
T_T0CLRI                       EQU       T0CLRI    -T0BASE    

T0LD_OFFSET                    EQU       0x0300
T0VAL_OFFSET                   EQU       0x0304
T0CON_OFFSET                   EQU       0x0308
T0CLRI_OFFSET                  EQU       0x030C

; GENERAL PURPOSE TIMER

T1BASE                         EQU       0xFFFF0320
T1LD                           EQU       0xFFFF0320
T1VAL                          EQU       0xFFFF0324
T1CON                          EQU       0xFFFF0328
T1CLRI                         EQU       0xFFFF032C
T1CAP                          EQU       0xFFFF0330
Z_T1LD                         EQU       T1LD      -Z_BASE
Z_T1VAL                        EQU       T1VAL     -Z_BASE
Z_T1CON                        EQU       T1CON     -Z_BASE
Z_T1CLRI                       EQU       T1CLRI    -Z_BASE
Z_T1CAP                        EQU       T1CAP     -Z_BASE

T_T1LD                         EQU       T1LD      -T1BASE    
T_T1VAL                        EQU       T1VAL     -T1BASE    
T_T1CON                        EQU       T1CON     -T1BASE    
T_T1CLRI                       EQU       T1CLRI    -T1BASE    
T_T1CAP                        EQU       T1CAP     -T1BASE    

T1LD_OFFSET                    EQU       0x0320
T1VAL_OFFSET                   EQU       0x0324
T1CON_OFFSET                   EQU       0x0328
T1CLRI_OFFSET                  EQU       0x032C
T1CAP_OFFSET                   EQU       0x0330

; WATCHDOG TIMER

T3BASE                         EQU       0xFFFF0360
T3LD                           EQU       0xFFFF0360
T3VAL                          EQU       0xFFFF0364
T3CON                          EQU       0xFFFF0368
T3CLRI                         EQU       0xFFFF036C
Z_T3LD                         EQU       T3LD      -Z_BASE
Z_T3VAL                        EQU       T3VAL     -Z_BASE
Z_T3CON                        EQU       T3CON     -Z_BASE
Z_T3CLRI                       EQU       T3CLRI    -Z_BASE

T_T3LD                         EQU       T3LD      -T3BASE    
T_T3VAL                        EQU       T3VAL     -T3BASE    
T_T3CON                        EQU       T3CON     -T3BASE    
T_T3CLRI                       EQU       T3CLRI    -T3BASE    

T3LD_OFFSET                    EQU       0x0360
T3VAL_OFFSET                   EQU       0x0364
T3CON_OFFSET                   EQU       0x0368
T3CLRI_OFFSET                  EQU       0x036C

; PLL AND OSCILLATOR CONTROL

PLLBASE                        EQU       0xFFFF0400
PLLSTA                         EQU       0xFFFF0400
POWKEY1                        EQU       0xFFFF0404
POWCON                         EQU       0xFFFF0408
POWKEY2                        EQU       0xFFFF040C
PLLKEY1                        EQU       0xFFFF0410
PLLCON                         EQU       0xFFFF0414
PLLKEY2                        EQU       0xFFFF0418
Z_PLLSTA                       EQU       PLLSTA    -Z_BASE
Z_POWKEY1                      EQU       POWKEY1   -Z_BASE
Z_POWCON                       EQU       POWCON    -Z_BASE
Z_POWKEY2                      EQU       POWKEY2   -Z_BASE
Z_PLLKEY1                      EQU       PLLKEY1   -Z_BASE
Z_PLLCON                       EQU       PLLCON    -Z_BASE
Z_PLLKEY2                      EQU       PLLKEY2   -Z_BASE

T_PLLSTA                       EQU       PLLSTA    -PLLBASE   
T_POWKEY1                      EQU       POWKEY1   -PLLBASE   
T_POWCON                       EQU       POWCON    -PLLBASE   
T_POWKEY2                      EQU       POWKEY2   -PLLBASE   
T_PLLKEY1                      EQU       PLLKEY1   -PLLBASE   
T_PLLCON                       EQU       PLLCON    -PLLBASE   
T_PLLKEY2                      EQU       PLLKEY2   -PLLBASE   

PLLSTA_OFFSET                  EQU       0x0400
POWKEY1_OFFSET                 EQU       0x0404
POWCON_OFFSET                  EQU       0x0408
POWKEY2_OFFSET                 EQU       0x040C
PLLKEY1_OFFSET                 EQU       0x0410
PLLCON_OFFSET                  EQU       0x0414
PLLKEY2_OFFSET                 EQU       0x0418

; GLOBAL PERIPHERAL CONTROL

ALLBASE                        EQU       0xFFFF0434
POWKEY3                        EQU       0xFFFF0434
POWCON1                        EQU       0xFFFF0438
POWKEY4                        EQU       0xFFFF043C
Z_POWKEY3                      EQU       POWKEY3   -Z_BASE
Z_POWCON1                      EQU       POWCON1   -Z_BASE
Z_POWKEY4                      EQU       POWKEY4   -Z_BASE

T_POWKEY3                      EQU       POWKEY3   -ALLBASE   
T_POWCON1                      EQU       POWCON1   -ALLBASE   
T_POWKEY4                      EQU       POWKEY4   -ALLBASE   

POWKEY3_OFFSET                 EQU       0x0434
POWCON1_OFFSET                 EQU       0x0438
POWKEY4_OFFSET                 EQU       0x043C

; POWER SUPPLY MONITOR

PSMBASE                        EQU       0xFFFF0440
PSMCON                         EQU       0xFFFF0440
CMPCON                         EQU       0xFFFF0444
Z_PSMCON                       EQU       PSMCON    -Z_BASE
Z_CMPCON                       EQU       CMPCON    -Z_BASE

T_PSMCON                       EQU       PSMCON    -PSMBASE   
T_CMPCON                       EQU       CMPCON    -PSMBASE   

PSMCON_OFFSET                  EQU       0x0440
CMPCON_OFFSET                  EQU       0x0444

; Band Gap Reference

REFBASE                        EQU       0xFFFF0480
REFCON                         EQU       0xFFFF048C
Z_REFCON                       EQU       REFCON    -Z_BASE

T_REFCON                       EQU       REFCON    -REFBASE   

REFCON_OFFSET                  EQU       0x048C

; ADC INTERFACE REGISTERS

ADCBASE                        EQU       0xFFFF0500
ADCCON                         EQU       0xFFFF0500
ADCCP                          EQU       0xFFFF0504
ADCCN                          EQU       0xFFFF0508
ADCSTA                         EQU       0xFFFF050C
ADCDAT                         EQU       0xFFFF0510
ADCRST                         EQU       0xFFFF0514
ADCGN                          EQU       0xFFFF0530
ADCOF                          EQU       0xFFFF0534
Z_ADCCON                       EQU       ADCCON    -Z_BASE
Z_ADCCP                        EQU       ADCCP     -Z_BASE
Z_ADCCN                        EQU       ADCCN     -Z_BASE
Z_ADCSTA                       EQU       ADCSTA    -Z_BASE
Z_ADCDAT                       EQU       ADCDAT    -Z_BASE
Z_ADCRST                       EQU       ADCRST    -Z_BASE
Z_ADCGN                        EQU       ADCGN     -Z_BASE
Z_ADCOF                        EQU       ADCOF     -Z_BASE

T_ADCCON                       EQU       ADCCON    -ADCBASE   
T_ADCCP                        EQU       ADCCP     -ADCBASE   
T_ADCCN                        EQU       ADCCN     -ADCBASE   
T_ADCSTA                       EQU       ADCSTA    -ADCBASE   
T_ADCDAT                       EQU       ADCDAT    -ADCBASE   
T_ADCRST                       EQU       ADCRST    -ADCBASE   
T_ADCGN                        EQU       ADCGN     -ADCBASE   
T_ADCOF                        EQU       ADCOF     -ADCBASE   

ADCCON_OFFSET                  EQU       0x0500
ADCCP_OFFSET                   EQU       0x0504
ADCCN_OFFSET                   EQU       0x0508
ADCSTA_OFFSET                  EQU       0x050C
ADCDAT_OFFSET                  EQU       0x0510
ADCRST_OFFSET                  EQU       0x0514
ADCGN_OFFSET                   EQU       0x0530
ADCOF_OFFSET                   EQU       0x0534

; DAC INTERFACE REGISTERS

DACBASE                        EQU       0xFFFF0600
DAC0CON                        EQU       0xFFFF0600
DAC0DAT                        EQU       0xFFFF0604
DAC1CON                        EQU       0xFFFF0608
DAC1DAT                        EQU       0xFFFF060C
DAC2CON                        EQU       0xFFFF0610
DAC2DAT                        EQU       0xFFFF0614
DAC3CON                        EQU       0xFFFF0618
DAC3DAT                        EQU       0xFFFF061C
Z_DAC0CON                      EQU       DAC0CON   -Z_BASE
Z_DAC0DAT                      EQU       DAC0DAT   -Z_BASE
Z_DAC1CON                      EQU       DAC1CON   -Z_BASE
Z_DAC1DAT                      EQU       DAC1DAT   -Z_BASE
Z_DAC2CON                      EQU       DAC2CON   -Z_BASE
Z_DAC2DAT                      EQU       DAC2DAT   -Z_BASE
Z_DAC3CON                      EQU       DAC3CON   -Z_BASE
Z_DAC3DAT                      EQU       DAC3DAT   -Z_BASE

T_DAC0CON                      EQU       DAC0CON   -DACBASE   
T_DAC0DAT                      EQU       DAC0DAT   -DACBASE   
T_DAC1CON                      EQU       DAC1CON   -DACBASE   
T_DAC1DAT                      EQU       DAC1DAT   -DACBASE   
T_DAC2CON                      EQU       DAC2CON   -DACBASE   
T_DAC2DAT                      EQU       DAC2DAT   -DACBASE   
T_DAC3CON                      EQU       DAC3CON   -DACBASE   
T_DAC3DAT                      EQU       DAC3DAT   -DACBASE   

DAC0CON_OFFSET                 EQU       0x0600
DAC0DAT_OFFSET                 EQU       0x0604
DAC1CON_OFFSET                 EQU       0x0608
DAC1DAT_OFFSET                 EQU       0x060C
DAC2CON_OFFSET                 EQU       0x0610
DAC2DAT_OFFSET                 EQU       0x0614
DAC3CON_OFFSET                 EQU       0x0618
DAC3DAT_OFFSET                 EQU       0x061C

; I2C0 BUS PERIPHERAL DEVICE 0

I2C0BASE                       EQU       0xFFFF0800
I2C0MCON                       EQU       0xFFFF0800
I2C0MSTA                       EQU       0xFFFF0804
I2C0MRX                        EQU       0xFFFF0808
I2C0MTX                        EQU       0xFFFF080C
I2C0MCNT0                      EQU       0xFFFF0810
I2C0MCNT1                      EQU       0xFFFF0814
I2C0ADR0                       EQU       0xFFFF0818
I2C0DIV                        EQU       0xFFFF0824
I2C0SCON                       EQU       0xFFFF0828
I2C0SSTA                       EQU       0xFFFF082C
I2C0SRX                        EQU       0xFFFF0830
I2C0STX                        EQU       0xFFFF0834
I2C0ALT                        EQU       0xFFFF0838
I2C0ID0                        EQU       0xFFFF083C
I2C0ID1                        EQU       0xFFFF0840
I2C0ID2                        EQU       0xFFFF0844
I2C0ID3                        EQU       0xFFFF0848
I2C0FSTA                       EQU       0xFFFF084C
Z_I2C0MCON                     EQU       I2C0MCON  -Z_BASE
Z_I2C0MSTA                     EQU       I2C0MSTA  -Z_BASE
Z_I2C0MRX                      EQU       I2C0MRX   -Z_BASE
Z_I2C0MTX                      EQU       I2C0MTX   -Z_BASE
Z_I2C0MCNT0                    EQU       I2C0MCNT0 -Z_BASE
Z_I2C0MCNT1                    EQU       I2C0MCNT1 -Z_BASE
Z_I2C0ADR0                     EQU       I2C0ADR0  -Z_BASE
Z_I2C0DIV                      EQU       I2C0DIV   -Z_BASE
Z_I2C0SCON                     EQU       I2C0SCON  -Z_BASE
Z_I2C0SSTA                     EQU       I2C0SSTA  -Z_BASE
Z_I2C0SRX                      EQU       I2C0SRX   -Z_BASE
Z_I2C0STX                      EQU       I2C0STX   -Z_BASE
Z_I2C0ALT                      EQU       I2C0ALT   -Z_BASE
Z_I2C0ID0                      EQU       I2C0ID0   -Z_BASE
Z_I2C0ID1                      EQU       I2C0ID1   -Z_BASE
Z_I2C0ID2                      EQU       I2C0ID2   -Z_BASE
Z_I2C0ID3                      EQU       I2C0ID3   -Z_BASE
Z_I2C0FSTA                     EQU       I2C0FSTA  -Z_BASE

T_I2C0MCON                     EQU       I2C0MCON  -I2C0BASE  
T_I2C0MSTA                     EQU       I2C0MSTA  -I2C0BASE  
T_I2C0MRX                      EQU       I2C0MRX   -I2C0BASE  
T_I2C0MTX                      EQU       I2C0MTX   -I2C0BASE  
T_I2C0MCNT0                    EQU       I2C0MCNT0 -I2C0BASE  
T_I2C0MCNT1                    EQU       I2C0MCNT1 -I2C0BASE  
T_I2C0ADR0                     EQU       I2C0ADR0  -I2C0BASE  
T_I2C0DIV                      EQU       I2C0DIV   -I2C0BASE  
T_I2C0SCON                     EQU       I2C0SCON  -I2C0BASE  
T_I2C0SSTA                     EQU       I2C0SSTA  -I2C0BASE  
T_I2C0SRX                      EQU       I2C0SRX   -I2C0BASE  
T_I2C0STX                      EQU       I2C0STX   -I2C0BASE  
T_I2C0ALT                      EQU       I2C0ALT   -I2C0BASE  
T_I2C0ID0                      EQU       I2C0ID0   -I2C0BASE  
T_I2C0ID1                      EQU       I2C0ID1   -I2C0BASE  
T_I2C0ID2                      EQU       I2C0ID2   -I2C0BASE  
T_I2C0ID3                      EQU       I2C0ID3   -I2C0BASE  
T_I2C0FSTA                     EQU       I2C0FSTA  -I2C0BASE  

I2C0MCON_OFFSET                EQU       0x0800
I2C0MSTA_OFFSET                EQU       0x0804
I2C0MRX_OFFSET                 EQU       0x0808
I2C0MTX_OFFSET                 EQU       0x080C
I2C0MCNT0_OFFSET               EQU       0x0810
I2C0MCNT1_OFFSET               EQU       0x0814
I2C0ADR0_OFFSET                EQU       0x0818
I2C0DIV_OFFSET                 EQU       0x0824
I2C0SCON_OFFSET                EQU       0x0828
I2C0SSTA_OFFSET                EQU       0x082C
I2C0SRX_OFFSET                 EQU       0x0830
I2C0STX_OFFSET                 EQU       0x0834
I2C0ALT_OFFSET                 EQU       0x0838
I2C0ID0_OFFSET                 EQU       0x083C
I2C0ID1_OFFSET                 EQU       0x0840
I2C0ID2_OFFSET                 EQU       0x0844
I2C0ID3_OFFSET                 EQU       0x0848
I2C0FSTA_OFFSET                EQU       0x084C

; I2C1 BUS PERIPHERAL DEVICE 0

;I2C0BASE                       EQU       0xFFFF0900
I2C1MCON                       EQU       0xFFFF0900
I2C1MSTA                       EQU       0xFFFF0904
I2C1MRX                        EQU       0xFFFF0908
I2C1MTX                        EQU       0xFFFF090C
I2C1MCNT0                      EQU       0xFFFF0910
I2C1MCNT1                      EQU       0xFFFF0914
I2C1ADR0                       EQU       0xFFFF0918
I2C1DIV                        EQU       0xFFFF0924
I2C1SCON                       EQU       0xFFFF0828
I2C1SSTA                       EQU       0xFFFF092C
I2C1SRX                        EQU       0xFFFF0930
I2C1STX                        EQU       0xFFFF0934
I2C1ALT                        EQU       0xFFFF0938
I2C1ID0                        EQU       0xFFFF093C
I2C1ID1                        EQU       0xFFFF0940
I2C1ID2                        EQU       0xFFFF0944
I2C1ID3                        EQU       0xFFFF0948
I2C1FSTA                       EQU       0xFFFF094C
Z_I2C1MCON                     EQU       I2C1MCON  -Z_BASE
Z_I2C1MSTA                     EQU       I2C1MSTA  -Z_BASE
Z_I2C1MRX                      EQU       I2C1MRX   -Z_BASE
Z_I2C1MTX                      EQU       I2C1MTX   -Z_BASE
Z_I2C1MCNT0                    EQU       I2C1MCNT0 -Z_BASE
Z_I2C1MCNT1                    EQU       I2C1MCNT1 -Z_BASE
Z_I2C1ADR0                     EQU       I2C1ADR0  -Z_BASE
Z_I2C1DIV                      EQU       I2C1DIV   -Z_BASE
Z_I2C1SCON                     EQU       I2C1SCON  -Z_BASE
Z_I2C1SSTA                     EQU       I2C1SSTA  -Z_BASE
Z_I2C1SRX                      EQU       I2C1SRX   -Z_BASE
Z_I2C1STX                      EQU       I2C1STX   -Z_BASE
Z_I2C1ALT                      EQU       I2C1ALT   -Z_BASE
Z_I2C1ID0                      EQU       I2C1ID0   -Z_BASE
Z_I2C1ID1                      EQU       I2C1ID1   -Z_BASE
Z_I2C1ID2                      EQU       I2C1ID2   -Z_BASE
Z_I2C1ID3                      EQU       I2C1ID3   -Z_BASE
Z_I2C1FSTA                     EQU       I2C1FSTA  -Z_BASE

T_I2C1MCON                     EQU       I2C1MCON  -I2C1BASE  
T_I2C1MSTA                     EQU       I2C1MSTA  -I2C1BASE  
T_I2C1MRX                      EQU       I2C1MRX   -I2C1BASE  
T_I2C1MTX                      EQU       I2C1MTX   -I2C1BASE  
T_I2C1MCNT0                    EQU       I2C1MCNT0 -I2C1BASE  
T_I2C1MCNT1                    EQU       I2C1MCNT1 -I2C1BASE  
T_I2C1ADR0                     EQU       I2C1ADR0  -I2C1BASE  
T_I2C1DIV                      EQU       I2C1DIV   -I2C1BASE  
T_I2C1SCON                     EQU       I2C1SCON  -I2C1BASE  
T_I2C1SSTA                     EQU       I2C1SSTA  -I2C1BASE  
T_I2C1SRX                      EQU       I2C1SRX   -I2C1BASE  
T_I2C1STX                      EQU       I2C1STX   -I2C1BASE  
T_I2C1ALT                      EQU       I2C1ALT   -I2C1BASE  
T_I2C1ID0                      EQU       I2C1ID0   -I2C1BASE  
T_I2C1ID1                      EQU       I2C1ID1   -I2C1BASE  
T_I2C1ID2                      EQU       I2C1ID2   -I2C1BASE  
T_I2C1ID3                      EQU       I2C1ID3   -I2C1BASE  
T_I2C1FSTA                     EQU       I2C1FSTA  -I2C1BASE  

I2C1MCON_OFFSET                EQU       0x0900
I2C1MSTA_OFFSET                EQU       0x0904
I2C1MRX_OFFSET                 EQU       0x0908
I2C1MTX_OFFSET                 EQU       0x090C
I2C1MCNT0_OFFSET               EQU       0x0910
I2C1MCNT1_OFFSET               EQU       0x0914
I2C1ADR0_OFFSET                EQU       0x0918
I2C1DIV_OFFSET                 EQU       0x0924
I2C1SCON_OFFSET                EQU       0x0828
I2C1SSTA_OFFSET                EQU       0x092C
I2C1SRX_OFFSET                 EQU       0x0930
I2C1STX_OFFSET                 EQU       0x0934
I2C1ALT_OFFSET                 EQU       0x0938
I2C1ID0_OFFSET                 EQU       0x093C
I2C1ID1_OFFSET                 EQU       0x0940
I2C1ID2_OFFSET                 EQU       0x0944
I2C1ID3_OFFSET                 EQU       0x0948
I2C1FSTA_OFFSET                EQU       0x094C

; SERIAL PORT INTERFACE PERIPHERAL

SPIBASE                        EQU       0xFFFF0A00
SPISTA                         EQU       0xFFFF0A00
SPIRX                          EQU       0xFFFF0A04
SPITX                          EQU       0xFFFF0A08
SPIDIV                         EQU       0xFFFF0A0C
SPICON                         EQU       0xFFFF0A10
Z_SPISTA                       EQU       SPISTA    -Z_BASE
Z_SPIRX                        EQU       SPIRX     -Z_BASE
Z_SPITX                        EQU       SPITX     -Z_BASE
Z_SPIDIV                       EQU       SPIDIV    -Z_BASE
Z_SPICON                       EQU       SPICON    -Z_BASE

T_SPISTA                       EQU       SPISTA    -SPIBASE   
T_SPIRX                        EQU       SPIRX     -SPIBASE   
T_SPITX                        EQU       SPITX     -SPIBASE   
T_SPIDIV                       EQU       SPIDIV    -SPIBASE   
T_SPICON                       EQU       SPICON    -SPIBASE   

SPISTA_OFFSET                  EQU       0x0A00
SPIRX_OFFSET                   EQU       0x0A04
SPITX_OFFSET                   EQU       0x0A08
SPIDIV_OFFSET                  EQU       0x0A0C
SPICON_OFFSET                  EQU       0x0A10

; PROGRAMABLE LOGIC ARRAY

PLABASE                        EQU       0xFFFF0B00
PLAELM0                        EQU       0xFFFF0B00
PLAELM1                        EQU       0xFFFF0B04
PLAELM2                        EQU       0xFFFF0B08
PLAELM3                        EQU       0xFFFF0B0C
PLAELM4                        EQU       0xFFFF0B10
PLAELM5                        EQU       0xFFFF0B14
PLAELM6                        EQU       0xFFFF0B18
PLAELM7                        EQU       0xFFFF0B1C
PLAELM8                        EQU       0xFFFF0B20
PLAELM9                        EQU       0xFFFF0B24
PLAELM10                       EQU       0xFFFF0B28
PLAELM11                       EQU       0xFFFF0B2C
PLAELM12                       EQU       0xFFFF0B30
PLAELM13                       EQU       0xFFFF0B34
PLAELM14                       EQU       0xFFFF0B38
PLAELM15                       EQU       0xFFFF0B3C
PLACLK                         EQU       0xFFFF0B40
PLAIRQ                         EQU       0xFFFF0B44
PLAADC                         EQU       0xFFFF0B48
PLADIN                         EQU       0xFFFF0B4C
PLADOUT                        EQU       0xFFFF0B50
PLALCK                         EQU       0xFFFF0B54
      
; "PLADLCK" has been deprecated. Use "PLALCK" instead.
PLADLCK                        EQU       0xFFFF0B54
;	ENDIF
Z_PLAELM0                      EQU       PLAELM0   -Z_BASE
Z_PLAELM1                      EQU       PLAELM1   -Z_BASE
Z_PLAELM2                      EQU       PLAELM2   -Z_BASE
Z_PLAELM3                      EQU       PLAELM3   -Z_BASE
Z_PLAELM4                      EQU       PLAELM4   -Z_BASE
Z_PLAELM5                      EQU       PLAELM5   -Z_BASE
Z_PLAELM6                      EQU       PLAELM6   -Z_BASE
Z_PLAELM7                      EQU       PLAELM7   -Z_BASE
Z_PLAELM8                      EQU       PLAELM8   -Z_BASE
Z_PLAELM9                      EQU       PLAELM9   -Z_BASE
Z_PLAELM10                     EQU       PLAELM10  -Z_BASE
Z_PLAELM11                     EQU       PLAELM11  -Z_BASE
Z_PLAELM12                     EQU       PLAELM12  -Z_BASE
Z_PLAELM13                     EQU       PLAELM13  -Z_BASE
Z_PLAELM14                     EQU       PLAELM14  -Z_BASE
Z_PLAELM15                     EQU       PLAELM15  -Z_BASE
Z_PLACLK                       EQU       PLACLK    -Z_BASE
Z_PLAIRQ                       EQU       PLAIRQ    -Z_BASE
Z_PLAADC                       EQU       PLAADC    -Z_BASE
Z_PLADIN                       EQU       PLADIN    -Z_BASE
Z_PLADOUT                      EQU       PLADOUT   -Z_BASE
Z_PLALCK                       EQU       PLALCK    -Z_BASE
      
; "Z_PLADLCK" has been deprecated. Use "Z_PLALCK" instead.
Z_PLADLCK                      EQU       PLALCK    -Z_BASE
;	ENDIF

T_PLAELM0                      EQU       PLAELM0   -PLABASE   
T_PLAELM1                      EQU       PLAELM1   -PLABASE   
T_PLAELM2                      EQU       PLAELM2   -PLABASE   
T_PLAELM3                      EQU       PLAELM3   -PLABASE   
T_PLAELM4                      EQU       PLAELM4   -PLABASE   
T_PLAELM5                      EQU       PLAELM5   -PLABASE   
T_PLAELM6                      EQU       PLAELM6   -PLABASE   
T_PLAELM7                      EQU       PLAELM7   -PLABASE   
T_PLAELM8                      EQU       PLAELM8   -PLABASE   
T_PLAELM9                      EQU       PLAELM9   -PLABASE   
T_PLAELM10                     EQU       PLAELM10  -PLABASE   
T_PLAELM11                     EQU       PLAELM11  -PLABASE   
T_PLAELM12                     EQU       PLAELM12  -PLABASE   
T_PLAELM13                     EQU       PLAELM13  -PLABASE   
T_PLAELM14                     EQU       PLAELM14  -PLABASE   
T_PLAELM15                     EQU       PLAELM15  -PLABASE   
T_PLACLK                       EQU       PLACLK    -PLABASE   
T_PLAIRQ                       EQU       PLAIRQ    -PLABASE   
T_PLAADC                       EQU       PLAADC    -PLABASE   
T_PLADIN                       EQU       PLADIN    -PLABASE   
T_PLADOUT                      EQU       PLADOUT   -PLABASE   
T_PLALCK                       EQU       PLALCK    -PLABASE   
      
; "T_PLADLCK" has been deprecated. Use "T_PLALCK" instead.
T_PLADLCK                      EQU       PLALCK    -PLABASE   
;	ENDIF

PLAELM0_OFFSET                 EQU       0x0B00
PLAELM1_OFFSET                 EQU       0x0B04
PLAELM2_OFFSET                 EQU       0x0B08
PLAELM3_OFFSET                 EQU       0x0B0C
PLAELM4_OFFSET                 EQU       0x0B10
PLAELM5_OFFSET                 EQU       0x0B14
PLAELM6_OFFSET                 EQU       0x0B18
PLAELM7_OFFSET                 EQU       0x0B1C
PLAELM8_OFFSET                 EQU       0x0B20
PLAELM9_OFFSET                 EQU       0x0B24
PLAELM10_OFFSET                EQU       0x0B28
PLAELM11_OFFSET                EQU       0x0B2C
PLAELM12_OFFSET                EQU       0x0B30
PLAELM13_OFFSET                EQU       0x0B34
PLAELM14_OFFSET                EQU       0x0B38
PLAELM15_OFFSET                EQU       0x0B3C
PLACLK_OFFSET                  EQU       0x0B40
PLAIRQ_OFFSET                  EQU       0x0B44
PLAADC_OFFSET                  EQU       0x0B48
PLADIN_OFFSET                  EQU       0x0B4C
PLADOUT_OFFSET                 EQU       0x0B50
PLALCK_OFFSET                  EQU       0x0B54
     
; "PLADLCK_OFFSET" has been deprecated. Use "PLALCK_OFFSET" instead.
PLADLCK_OFFSET                 EQU       0xFFFF0B54
;	ENDIF

; PWM

PWMBASE                        EQU       0xFFFF0F80
PWMCON                         EQU       0xFFFF0F80
PWM0COM0                       EQU       0xFFFF0F84
PWM0COM1                       EQU       0xFFFF0F88
PWM0COM2                       EQU       0xFFFF0F8C
PWM0LEN                        EQU       0xFFFF0F90
PWM1COM0                       EQU       0xFFFF0F94
PWM1COM1                       EQU       0xFFFF0F98
PWM1COM2                       EQU       0xFFFF0F9C
PWM1LEN                        EQU       0xFFFF0FA0
PWM2COM0                       EQU       0xFFFF0FA4
PWM2COM1                       EQU       0xFFFF0FA8
PWM2COM2                       EQU       0xFFFF0FAC
PWM2LEN                        EQU       0xFFFF0FB0
PWMCLRI                        EQU       0xFFFF0FB8
Z_PWMCON                       EQU       PWMCON    -Z_BASE
Z_PWM0COM0                     EQU       PWM0COM0  -Z_BASE
Z_PWM0COM1                     EQU       PWM0COM1  -Z_BASE
Z_PWM0COM2                     EQU       PWM0COM2  -Z_BASE
Z_PWM0LEN                      EQU       PWM0LEN   -Z_BASE
Z_PWM1COM0                     EQU       PWM1COM0  -Z_BASE
Z_PWM1COM1                     EQU       PWM1COM1  -Z_BASE
Z_PWM1COM2                     EQU       PWM1COM2  -Z_BASE
Z_PWM1LEN                      EQU       PWM1LEN   -Z_BASE
Z_PWM2COM0                     EQU       PWM2COM0  -Z_BASE
Z_PWM2COM1                     EQU       PWM2COM1  -Z_BASE
Z_PWM2COM2                     EQU       PWM2COM2  -Z_BASE
Z_PWM2LEN                      EQU       PWM2LEN   -Z_BASE
Z_PWMCLRI                      EQU       PWMCLRI   -Z_BASE

T_PWMCON                       EQU       PWMCON    -PWMBASE   
T_PWM0COM0                     EQU       PWM0COM0  -PWMBASE   
T_PWM0COM1                     EQU       PWM0COM1  -PWMBASE   
T_PWM0COM2                     EQU       PWM0COM2  -PWMBASE   
T_PWM0LEN                      EQU       PWM0LEN   -PWMBASE   
T_PWM1COM0                     EQU       PWM1COM0  -PWMBASE   
T_PWM1COM1                     EQU       PWM1COM1  -PWMBASE   
T_PWM1COM2                     EQU       PWM1COM2  -PWMBASE   
T_PWM1LEN                      EQU       PWM1LEN   -PWMBASE   
T_PWM2COM0                     EQU       PWM2COM0  -PWMBASE   
T_PWM2COM1                     EQU       PWM2COM1  -PWMBASE   
T_PWM2COM2                     EQU       PWM2COM2  -PWMBASE   
T_PWM2LEN                      EQU       PWM2LEN   -PWMBASE   
T_PWMCLRI                      EQU       PWMCLRI   -PWMBASE   

PWMCON_OFFSET                  EQU       0x0F80
PWM0COM0_OFFSET                EQU       0x0F84
PWM0COM1_OFFSET                EQU       0x0F88
PWM0COM2_OFFSET                EQU       0x0F8C
PWM0LEN_OFFSET                 EQU       0x0F90
PWM1COM0_OFFSET                EQU       0x0F94
PWM1COM1_OFFSET                EQU       0x0F98
PWM1COM2_OFFSET                EQU       0x0F9C
PWM1LEN_OFFSET                 EQU       0x0FA0
PWM2COM0_OFFSET                EQU       0x0FA4
PWM2COM1_OFFSET                EQU       0x0FA8
PWM2COM2_OFFSET                EQU       0x0FAC
PWM2LEN_OFFSET                 EQU       0x0FB0
PWMCLRI_OFFSET                 EQU       0x0FB8

; GPIO AND SERIAL PORT MUX

GPIOBASE                       EQU       0xFFFFF400
GP0CON                         EQU       0xFFFFF400
GP1CON                         EQU       0xFFFFF404
GP2CON                         EQU       0xFFFFF408
GP0DAT                         EQU       0xFFFFF420
GP0SET                         EQU       0xFFFFF424
GP0CLR                         EQU       0xFFFFF428
GP0PAR                         EQU       0xFFFFF42C
GP1DAT                         EQU       0xFFFFF430
GP1SET                         EQU       0xFFFFF434
GP1CLR                         EQU       0xFFFFF438
GP1PAR                         EQU       0xFFFFF43C
GP2DAT                         EQU       0xFFFFF440
GP2SET                         EQU       0xFFFFF444
GP2CLR                         EQU       0xFFFFF448
GP2PAR                         EQU       0xFFFFF44C
Z_GP0CON                       EQU       GP0CON    -Z_BASE
Z_GP1CON                       EQU       GP1CON    -Z_BASE
Z_GP2CON                       EQU       GP2CON    -Z_BASE
Z_GP0DAT                       EQU       GP0DAT    -Z_BASE
Z_GP0SET                       EQU       GP0SET    -Z_BASE
Z_GP0CLR                       EQU       GP0CLR    -Z_BASE
Z_GP0PAR                       EQU       GP0PAR    -Z_BASE
Z_GP1DAT                       EQU       GP1DAT    -Z_BASE
Z_GP1SET                       EQU       GP1SET    -Z_BASE
Z_GP1CLR                       EQU       GP1CLR    -Z_BASE
Z_GP1PAR                       EQU       GP1PAR    -Z_BASE
Z_GP2DAT                       EQU       GP2DAT    -Z_BASE
Z_GP2SET                       EQU       GP2SET    -Z_BASE
Z_GP2CLR                       EQU       GP2CLR    -Z_BASE
Z_GP2PAR                       EQU       GP2PAR    -Z_BASE

T_GP0CON                       EQU       GP0CON    -GPIOBASE  
T_GP1CON                       EQU       GP1CON    -GPIOBASE  
T_GP2CON                       EQU       GP2CON    -GPIOBASE  
T_GP0DAT                       EQU       GP0DAT    -GPIOBASE  
T_GP0SET                       EQU       GP0SET    -GPIOBASE  
T_GP0CLR                       EQU       GP0CLR    -GPIOBASE  
T_GP0PAR                       EQU       GP0PAR    -GPIOBASE  
T_GP1DAT                       EQU       GP1DAT    -GPIOBASE  
T_GP1SET                       EQU       GP1SET    -GPIOBASE  
T_GP1CLR                       EQU       GP1CLR    -GPIOBASE  
T_GP1PAR                       EQU       GP1PAR    -GPIOBASE  
T_GP2DAT                       EQU       GP2DAT    -GPIOBASE  
T_GP2SET                       EQU       GP2SET    -GPIOBASE  
T_GP2CLR                       EQU       GP2CLR    -GPIOBASE  
T_GP2PAR                       EQU       GP2PAR    -GPIOBASE  

GP0CON_OFFSET                  EQU       0x0400
GP1CON_OFFSET                  EQU       0x0404
GP2CON_OFFSET                  EQU       0x0408
GP0DAT_OFFSET                  EQU       0x0420
GP0SET_OFFSET                  EQU       0x0424
GP0CLR_OFFSET                  EQU       0x0428
GP0PAR_OFFSET                  EQU       0x042C
GP1DAT_OFFSET                  EQU       0x0430
GP1SET_OFFSET                  EQU       0x0434
GP1CLR_OFFSET                  EQU       0x0438
GP1PAR_OFFSET                  EQU       0x043C
GP2DAT_OFFSET                  EQU       0x0440
GP2SET_OFFSET                  EQU       0x0444
GP2CLR_OFFSET                  EQU       0x0448
GP2PAR_OFFSET                  EQU       0x044C

; FLASH CONTROL INTERFACE

FLASHBASE                      EQU       0xFFFFF800
FEESTA                         EQU       0xFFFFF800
FEEMOD                         EQU       0xFFFFF804
FEECON                         EQU       0xFFFFF808
FEEDAT                         EQU       0xFFFFF80C
FEEADR                         EQU       0xFFFFF810
FEESIGN                        EQU       0xFFFFF818
FEEPRO                         EQU       0xFFFFF81C
FEEHIDE                        EQU       0xFFFFF820
Z_FEESTA                       EQU       FEESTA    -Z_BASE
Z_FEEMOD                       EQU       FEEMOD    -Z_BASE
Z_FEECON                       EQU       FEECON    -Z_BASE
Z_FEEDAT                       EQU       FEEDAT    -Z_BASE
Z_FEEADR                       EQU       FEEADR    -Z_BASE
Z_FEESIGN                      EQU       FEESIGN   -Z_BASE
Z_FEEPRO                       EQU       FEEPRO    -Z_BASE
Z_FEEHIDE                      EQU       FEEHIDE   -Z_BASE

T_FEESTA                       EQU       FEESTA    -FLASHBASE 
T_FEEMOD                       EQU       FEEMOD    -FLASHBASE 
T_FEECON                       EQU       FEECON    -FLASHBASE 
T_FEEDAT                       EQU       FEEDAT    -FLASHBASE 
T_FEEADR                       EQU       FEEADR    -FLASHBASE 
T_FEESIGN                      EQU       FEESIGN   -FLASHBASE 
T_FEEPRO                       EQU       FEEPRO    -FLASHBASE 
T_FEEHIDE                      EQU       FEEHIDE   -FLASHBASE 

FEESTA_OFFSET                  EQU       0x0800
FEEMOD_OFFSET                  EQU       0x0804
FEECON_OFFSET                  EQU       0x0808
FEEDAT_OFFSET                  EQU       0x080C
FEEADR_OFFSET                  EQU       0x0810
FEESIGN_OFFSET                 EQU       0x0818
FEEPRO_OFFSET                  EQU       0x081C
FEEHIDE_OFFSET                 EQU       0x0820
	END

