Name |
Value |
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE |
4 |
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE |
4 |
C_S1_AXI_ENABLE |
0 |
C_S1_AXI_PROTOCOL |
AXI4 |
C_S1_AXI_ID_WIDTH |
4 |
C_S1_AXI_ADDR_WIDTH |
32 |
C_S1_AXI_DATA_WIDTH |
32 |
C_S1_AXI_SUPPORTS_READ |
1 |
C_S1_AXI_SUPPORTS_WRITE |
1 |
C_S1_AXI_SUPPORTS_NARROW_BURST |
1 |
C_S1_AXI_REG_EN0 |
0x00000 |
C_S1_AXI_REG_EN1 |
0x01000 |
C_S1_AXI_STRICT_COHERENCY |
1 |
C_S1_AXI_ENABLE_AP |
0 |
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE |
4 |
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE |
4 |
C_S2_AXI_ENABLE |
0 |
C_S2_AXI_PROTOCOL |
AXI4 |
C_S2_AXI_ID_WIDTH |
4 |
C_S2_AXI_ADDR_WIDTH |
32 |
C_S2_AXI_DATA_WIDTH |
32 |
C_S2_AXI_SUPPORTS_READ |
1 |
C_S2_AXI_SUPPORTS_WRITE |
1 |
C_S2_AXI_SUPPORTS_NARROW_BURST |
1 |
C_S2_AXI_REG_EN0 |
0x00000 |
C_S2_AXI_REG_EN1 |
0x01000 |
C_S2_AXI_STRICT_COHERENCY |
1 |
C_S2_AXI_ENABLE_AP |
0 |
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE |
4 |
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE |
4 |
C_S3_AXI_ENABLE |
0 |
C_S3_AXI_PROTOCOL |
AXI4 |
C_S3_AXI_ID_WIDTH |
4 |
C_S3_AXI_ADDR_WIDTH |
32 |
C_S3_AXI_DATA_WIDTH |
32 |
C_S3_AXI_SUPPORTS_READ |
1 |
C_S3_AXI_SUPPORTS_WRITE |
1 |
C_S3_AXI_SUPPORTS_NARROW_BURST |
1 |
C_S3_AXI_REG_EN0 |
0x00000 |
C_S3_AXI_REG_EN1 |
0x01000 |
C_S3_AXI_STRICT_COHERENCY |
1 |
C_S3_AXI_ENABLE_AP |
0 |
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE |
4 |
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE |
4 |
C_S4_AXI_ENABLE |
0 |
C_S4_AXI_PROTOCOL |
AXI4 |
C_S4_AXI_ID_WIDTH |
4 |
C_S4_AXI_ADDR_WIDTH |
32 |
C_S4_AXI_DATA_WIDTH |
32 |
C_S4_AXI_SUPPORTS_READ |
1 |
C_S4_AXI_SUPPORTS_WRITE |
1 |
C_S4_AXI_SUPPORTS_NARROW_BURST |
1 |
C_S4_AXI_REG_EN0 |
0x00000 |
C_S4_AXI_REG_EN1 |
0x01000 |
C_S4_AXI_STRICT_COHERENCY |
1 |
C_S4_AXI_ENABLE_AP |
0 |
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE |
4 |
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE |
4 |
C_S5_AXI_ENABLE |
0 |
C_S5_AXI_PROTOCOL |
AXI4 |
C_S5_AXI_ID_WIDTH |
4 |
C_S5_AXI_ADDR_WIDTH |
32 |
C_S5_AXI_DATA_WIDTH |
32 |
C_S5_AXI_SUPPORTS_READ |
1 |
C_S5_AXI_SUPPORTS_WRITE |
1 |
C_S5_AXI_SUPPORTS_NARROW_BURST |
1 |
C_S5_AXI_REG_EN0 |
0x00000 |
C_S5_AXI_REG_EN1 |
0x01000 |
C_S5_AXI_STRICT_COHERENCY |
1 |
C_S5_AXI_ENABLE_AP |
0 |
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE |
4 |
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE |
4 |
C_MCB_USE_EXTERNAL_BUFPLL |
0 |
C_SYS_RST_PRESENT |
0 |
C_INTERCONNECT_S0_AXI_MASTERS |
microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC |
C_INTERCONNECT_S0_AXI_AW_REGISTER |
8 |
C_INTERCONNECT_S0_AXI_AR_REGISTER |
8 |
C_INTERCONNECT_S0_AXI_W_REGISTER |
8 |
C_INTERCONNECT_S0_AXI_R_REGISTER |
8 |
C_INTERCONNECT_S0_AXI_B_REGISTER |
8 |