Project Statistics |
PROP_Board=Avnet Spartan-6 LX9 MicroBoard |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_ProjectDescription=This is the top-level wrapper around the Maxim Peripheral Module Microblaze system. It instantiates the microblaze, clocking, and a multiplexer to share the peripheral module ports amongst the I2C, SPI, GPIO, and UART Microblaze peripherals |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_VHDLSourceAnalysisStandard=VHDL-200X |
PROP_intProjectCreationTimestamp=2012-07-16T08:56:56 |
PROP_intWbtProjectID=1324A1C8D168464FA4AA3E97868C2DD5 |
PROP_intWbtProjectIteration=1 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxBitgStart_IntDone=true |
PROP_AutoTop=true |
PROP_DevFamily=Spartan6 |
PROP_DevDevice=xc6slx9 |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=csg324 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-2 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=1 |
FILE_VERILOG=2 |
FILE_XPS=1 |