Printable Version
Overview
Resources Used
1   MicroBlaze
2   Local Memory Bus (LMB) 1.0
2   AXI Interconnect
1   AXI to AXI Connector
1   Block RAM (BRAM) Block
2   LMB BRAM Controller
1   Digilent Shared Memory Bus Multiplexer
1   Processor System Reset Module
1   MicroBlaze Debug Module (MDM)
1   Clock Generator
5   AXI UART (Lite)
8   AXI General Purpose IO
4   AXI IIC Interface
4   AXI SPI Interface
Specifics
Generated Tue Sep 04 12:13:30 2012
EDK Version 13.4
Device Family spartan6
Device xc6slx16csg324-2

Block Diagram TOP

BlockDiagram
External Ports TOP

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
SHARED RESET I 1 RESET  RESET 
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_Wait_I_pin I 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_Wait_I
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_Mem_DQ IO 0:16 Digilent_Shared_Mem_Bus_Mux_Mem_DQ
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_CEN_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_CEN_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_RPN_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_RPN_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_Mem_Addr_O_pin O 0:25 Digilent_Shared_Mem_Bus_Mux_Mem_Addr_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_Mem_OEN_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_Mem_OEN_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_Mem_WEN_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_Mem_WEN_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_ADV_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_ADV_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CEN_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CEN_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CLK_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CLK_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CRE_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CRE_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_LB_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_LB_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_UB_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_UB_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_C_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_C_O
Digilent_Shared_Mem_Bus_Mux Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_S_O_pin O 1 Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_S_O
LEDS LEDS_TRI_O O 7:0 LEDS_GPIO_IO_O
axi_gpio_0 axi_gpio_0_GPIO_IO_I_pin I 7:0 axi_gpio_0_GPIO_IO_I
axi_gpio_0 axi_gpio_0_GPIO_IO_O_pin O 7:0 axi_gpio_0_GPIO_IO_O
axi_gpio_0 axi_gpio_0_GPIO_IO_T_pin O 7:0 axi_gpio_0_GPIO_IO_T
axi_gpio_1 axi_gpio_1_GPIO_IO_I_pin I 7:0 axi_gpio_1_GPIO_IO_I
axi_gpio_1 axi_gpio_1_GPIO_IO_O_pin O 7:0 axi_gpio_1_GPIO_IO_O
axi_gpio_1 axi_gpio_1_GPIO_IO_T_pin O 7:0 axi_gpio_1_GPIO_IO_T
axi_gpio_2 axi_gpio_2_GPIO_IO_I_pin I 7:0 axi_gpio_2_GPIO_IO_I
axi_gpio_2 axi_gpio_2_GPIO_IO_O_pin O 7:0 axi_gpio_2_GPIO_IO_O
axi_gpio_2 axi_gpio_2_GPIO_IO_T_pin O 7:0 axi_gpio_2_GPIO_IO_T
axi_gpio_3 axi_gpio_3_GPIO_IO_I_pin I 7:0 axi_gpio_3_GPIO_IO_I
axi_gpio_3 axi_gpio_3_GPIO_IO_O_pin O 7:0 axi_gpio_3_GPIO_IO_O
axi_gpio_3 axi_gpio_3_GPIO_IO_T_pin O 7:0 axi_gpio_3_GPIO_IO_T
axi_gpio_4 axi_gpio_4_GPIO_IO_I_pin I 7:0 axi_gpio_4_GPIO_IO_I
axi_gpio_4 axi_gpio_4_GPIO_IO_O_pin O 7:0 axi_gpio_4_GPIO_IO_O
axi_gpio_4 axi_gpio_4_GPIO_IO_T_pin O 7:0 axi_gpio_4_GPIO_IO_T
axi_gpio_5 axi_gpio_5_GPIO_IO_O_pin O 31:0 axi_gpio_5_GPIO_IO_O
axi_gpio_6 axi_gpio_6_GPIO_IO_I_pin I 31:0 net_axi_gpio_6_GPIO_IO_I_pin
axi_gpio_6 axi_gpio_6_GPIO_IO_O_pin O 31:0 axi_gpio_6_GPIO_IO_O
axi_iic_0 axi_iic_0_Scl_I_pin I 1 axi_iic_0_Scl_I
axi_iic_0 axi_iic_0_Sda_I_pin I 1 axi_iic_0_Sda_I
axi_iic_0 axi_iic_0_Scl_O_pin O 1 axi_iic_0_Scl_O
axi_iic_0 axi_iic_0_Scl_T_pin O 1 axi_iic_0_Scl_T
axi_iic_0 axi_iic_0_Sda_O_pin O 1 axi_iic_0_Sda_O
axi_iic_0 axi_iic_0_Sda_T_pin O 1 axi_iic_0_Sda_T
axi_iic_1 axi_iic_1_Scl_I_pin I 1 axi_iic_1_Scl_I
axi_iic_1 axi_iic_1_Sda_I_pin I 1 axi_iic_1_Sda_I
axi_iic_1 axi_iic_1_Scl_O_pin O 1 axi_iic_1_Scl_O
axi_iic_1 axi_iic_1_Scl_T_pin O 1 axi_iic_1_Scl_T
axi_iic_1 axi_iic_1_Sda_O_pin O 1 axi_iic_1_Sda_O
axi_iic_1 axi_iic_1_Sda_T_pin O 1 axi_iic_1_Sda_T
axi_iic_2 axi_iic_2_Scl_I_pin I 1 axi_iic_2_Scl_I
axi_iic_2 axi_iic_2_Sda_I_pin I 1 axi_iic_2_Sda_I
axi_iic_2 axi_iic_2_Scl_O_pin O 1 axi_iic_2_Scl_O
axi_iic_2 axi_iic_2_Scl_T_pin O 1 axi_iic_2_Scl_T
axi_iic_2 axi_iic_2_Sda_O_pin O 1 axi_iic_2_Sda_O
axi_iic_2 axi_iic_2_Sda_T_pin O 1 axi_iic_2_Sda_T
axi_iic_3 axi_iic_3_Scl_I_pin I 1 axi_iic_3_Scl_I
axi_iic_3 axi_iic_3_Sda_I_pin I 1 axi_iic_3_Sda_I
axi_iic_3 axi_iic_3_Scl_O_pin O 1 axi_iic_3_Scl_O
axi_iic_3 axi_iic_3_Scl_T_pin O 1 axi_iic_3_Scl_T
axi_iic_3 axi_iic_3_Sda_O_pin O 1 axi_iic_3_Sda_O
axi_iic_3 axi_iic_3_Sda_T_pin O 1 axi_iic_3_Sda_T
axi_spi_0 axi_spi_0_MISO_I_pin I 1 axi_spi_0_MISO_I
axi_spi_0 axi_spi_0_SPISEL_pin I 1 axi_spi_0_SPISEL
axi_spi_0 axi_spi_0_MOSI_O_pin O 1 axi_spi_0_MOSI_O
axi_spi_0 axi_spi_0_SCK_O_pin O 1 axi_spi_0_SCK_O
axi_spi_0 axi_spi_0_SS_O_pin O 0:0 axi_spi_0_SS_O
axi_spi_1 axi_spi_1_MISO_I_pin I 1 axi_spi_1_MISO_I
axi_spi_1 axi_spi_1_SPISEL_pin I 1 axi_spi_1_SPISEL
axi_spi_1 axi_spi_1_MOSI_O_pin O 1 axi_spi_1_MOSI_O
axi_spi_1 axi_spi_1_SCK_O_pin O 1 axi_spi_1_SCK_O
axi_spi_1 axi_spi_1_SS_O_pin O 0:0 axi_spi_1_SS_O
axi_spi_2 axi_spi_2_MISO_I_pin I 1 axi_spi_2_MISO_I
axi_spi_2 axi_spi_2_SPISEL_pin I 1 axi_spi_2_SPISEL
axi_spi_2 axi_spi_2_MOSI_O_pin O 1 axi_spi_2_MOSI_O
axi_spi_2 axi_spi_2_SCK_O_pin O 1 axi_spi_2_SCK_O
axi_spi_2 axi_spi_2_SS_O_pin O 0:0 axi_spi_2_SS_O
axi_spi_3 axi_spi_3_MISO_I_pin I 1 axi_spi_3_MISO_I
axi_spi_3 axi_spi_3_SPISEL_pin I 1 axi_spi_3_SPISEL
axi_spi_3 axi_spi_3_MOSI_O_pin O 1 axi_spi_3_MOSI_O
axi_spi_3 axi_spi_3_SCK_O_pin O 1 axi_spi_3_SCK_O
axi_spi_3 axi_spi_3_SS_O_pin O 0:0 axi_spi_3_SS_O
axi_uartlite_0 axi_uartlite_0_RX_pin I 1 axi_uartlite_0_RX
axi_uartlite_0 axi_uartlite_0_TX_pin O 1 axi_uartlite_0_TX
axi_uartlite_1 axi_uartlite_1_RX_pin I 1 axi_uartlite_1_RX
axi_uartlite_1 axi_uartlite_1_TX_pin O 1 axi_uartlite_1_TX
axi_uartlite_2 axi_uartlite_2_RX_pin I 1 axi_uartlite_2_RX
axi_uartlite_2 axi_uartlite_2_TX_pin O 1 axi_uartlite_2_TX
axi_uartlite_3 axi_uartlite_3_RX_pin I 1 axi_uartlite_3_RX
axi_uartlite_3 axi_uartlite_3_TX_pin O 1 axi_uartlite_3_TX
axi_uartlite_4 axi_uartlite_4_RX_pin I 1 RS232_Uart_1_sin
axi_uartlite_4 axi_uartlite_4_TX_pin O 1 RS232_Uart_1_sout
clock_generator_0 GCLK I 1 GCLK  CLK 


Processors TOP

microblaze_0   MicroBlaze
The MicroBlaze 32 bit soft processor

IP Specs
Core Version Documentation
microblaze 8.20.b IP


microblaze_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MB_RESET I 1 proc_sys_reset_0_MB_Reset
1 CLK I 1 clk_100_0000MHz
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
ILMB MASTER LMB microblaze_0_ilmb microblaze_0_i_bram_ctrl
DLMB MASTER LMB microblaze_0_dlmb microblaze_0_d_bram_ctrl
M_AXI_DP MASTER AXI axi4lite_0 16 Peripherals.
M_AXI_IP MASTER AXI axi4lite_0 16 Peripherals.
DEBUG TARGET XIL_MBDEBUG3 microblaze_0_debug debug_module


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SCO 0
C_FREQ 0
C_DATA_SIZE 32
C_DYNAMIC_BUS_SIZING 1
C_FAMILY virtex5
C_INSTANCE microblaze
C_AVOID_PRIMITIVES 0
C_FAULT_TOLERANT 0
C_ECC_USE_CE_EXCEPTION 0
C_LOCKSTEP_SLAVE 0
C_ENDIANNESS 0
C_AREA_OPTIMIZED 0
C_OPTIMIZATION 0
C_INTERCONNECT 2
C_STREAM_INTERCONNECT 0
C_DPLB_DWIDTH 32
C_DPLB_NATIVE_DWIDTH 32
C_DPLB_BURST_EN 0
C_DPLB_P2P 0
C_IPLB_DWIDTH 32
C_IPLB_NATIVE_DWIDTH 32
C_IPLB_BURST_EN 0
C_IPLB_P2P 0
C_M_AXI_DP_SUPPORTS_THREADS 0
C_M_AXI_DP_THREAD_ID_WIDTH 1
C_M_AXI_DP_SUPPORTS_READ 1
C_M_AXI_DP_SUPPORTS_WRITE 1
C_M_AXI_DP_SUPPORTS_NARROW_BURST 0
C_M_AXI_DP_DATA_WIDTH 32
C_M_AXI_DP_ADDR_WIDTH 32
C_M_AXI_DP_PROTOCOL AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS 0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING 1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING 1
C_M_AXI_IP_SUPPORTS_THREADS 0
C_M_AXI_IP_THREAD_ID_WIDTH 1
C_M_AXI_IP_SUPPORTS_READ 1
C_M_AXI_IP_SUPPORTS_WRITE 0
C_M_AXI_IP_SUPPORTS_NARROW_BURST 0
C_M_AXI_IP_DATA_WIDTH 32
C_M_AXI_IP_ADDR_WIDTH 32
C_M_AXI_IP_PROTOCOL AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING 1
C_D_AXI 0
C_D_PLB 0
C_D_LMB 1
C_I_AXI 0
C_I_PLB 0
C_I_LMB 1
C_USE_MSR_INSTR 1
C_USE_PCMP_INSTR 1
C_USE_BARREL 1
C_USE_DIV 0
C_USE_HW_MUL 1
C_USE_FPU 0
C_UNALIGNED_EXCEPTIONS 0
C_ILL_OPCODE_EXCEPTION 0
C_M_AXI_I_BUS_EXCEPTION 0
C_M_AXI_D_BUS_EXCEPTION 0
C_IPLB_BUS_EXCEPTION 0
C_DPLB_BUS_EXCEPTION 0
C_DIV_ZERO_EXCEPTION 0
C_FPU_EXCEPTION 0
C_FSL_EXCEPTION 0
C_USE_STACK_PROTECTION 0
C_PVR 0
C_PVR_USER1 0x00
C_PVR_USER2 0x00000000
C_DEBUG_ENABLED 1
C_NUMBER_OF_PC_BRK 1
C_NUMBER_OF_RD_ADDR_BRK 0
C_NUMBER_OF_WR_ADDR_BRK 0
C_INTERRUPT_IS_EDGE 0
C_EDGE_IS_POSITIVE 1
C_RESET_MSR 0x00000000
C_OPCODE_0x0_ILLEGAL 0
C_FSL_LINKS 0
C_FSL_DATA_SIZE 32
C_USE_EXTENDED_FSL_INSTR 0
C_M0_AXIS_PROTOCOL GENERIC
C_S0_AXIS_PROTOCOL GENERIC
C_M1_AXIS_PROTOCOL GENERIC
C_S1_AXIS_PROTOCOL GENERIC
C_M2_AXIS_PROTOCOL GENERIC
C_S2_AXIS_PROTOCOL GENERIC
C_M3_AXIS_PROTOCOL GENERIC
C_S3_AXIS_PROTOCOL GENERIC
C_M4_AXIS_PROTOCOL GENERIC
C_S4_AXIS_PROTOCOL GENERIC
C_M5_AXIS_PROTOCOL GENERIC
C_S5_AXIS_PROTOCOL GENERIC
C_M6_AXIS_PROTOCOL GENERIC
C_S6_AXIS_PROTOCOL GENERIC
C_M7_AXIS_PROTOCOL GENERIC
C_S7_AXIS_PROTOCOL GENERIC
C_M8_AXIS_PROTOCOL GENERIC
C_S8_AXIS_PROTOCOL GENERIC
C_M9_AXIS_PROTOCOL GENERIC
C_S9_AXIS_PROTOCOL GENERIC
C_M10_AXIS_PROTOCOL GENERIC
C_S10_AXIS_PROTOCOL GENERIC
C_M11_AXIS_PROTOCOL GENERIC
C_S11_AXIS_PROTOCOL GENERIC
C_M12_AXIS_PROTOCOL GENERIC
C_S12_AXIS_PROTOCOL GENERIC
C_M13_AXIS_PROTOCOL GENERIC
C_S13_AXIS_PROTOCOL GENERIC
C_M14_AXIS_PROTOCOL GENERIC
 
Name Value
C_S14_AXIS_PROTOCOL GENERIC
C_M15_AXIS_PROTOCOL GENERIC
C_S15_AXIS_PROTOCOL GENERIC
C_M0_AXIS_DATA_WIDTH 32
C_S0_AXIS_DATA_WIDTH 32
C_M1_AXIS_DATA_WIDTH 32
C_S1_AXIS_DATA_WIDTH 32
C_M2_AXIS_DATA_WIDTH 32
C_S2_AXIS_DATA_WIDTH 32
C_M3_AXIS_DATA_WIDTH 32
C_S3_AXIS_DATA_WIDTH 32
C_M4_AXIS_DATA_WIDTH 32
C_S4_AXIS_DATA_WIDTH 32
C_M5_AXIS_DATA_WIDTH 32
C_S5_AXIS_DATA_WIDTH 32
C_M6_AXIS_DATA_WIDTH 32
C_S6_AXIS_DATA_WIDTH 32
C_M7_AXIS_DATA_WIDTH 32
C_S7_AXIS_DATA_WIDTH 32
C_M8_AXIS_DATA_WIDTH 32
C_S8_AXIS_DATA_WIDTH 32
C_M9_AXIS_DATA_WIDTH 32
C_S9_AXIS_DATA_WIDTH 32
C_M10_AXIS_DATA_WIDTH 32
C_S10_AXIS_DATA_WIDTH 32
C_M11_AXIS_DATA_WIDTH 32
C_S11_AXIS_DATA_WIDTH 32
C_M12_AXIS_DATA_WIDTH 32
C_S12_AXIS_DATA_WIDTH 32
C_M13_AXIS_DATA_WIDTH 32
C_S13_AXIS_DATA_WIDTH 32
C_M14_AXIS_DATA_WIDTH 32
C_S14_AXIS_DATA_WIDTH 32
C_M15_AXIS_DATA_WIDTH 32
C_S15_AXIS_DATA_WIDTH 32
C_ICACHE_BASEADDR 0x00000000
C_ICACHE_HIGHADDR 0x3FFFFFFF
C_USE_ICACHE 0
C_ALLOW_ICACHE_WR 1
C_ADDR_TAG_BITS 17
C_CACHE_BYTE_SIZE 8192
C_ICACHE_USE_FSL 1
C_ICACHE_LINE_LEN 4
C_ICACHE_ALWAYS_USED 0
C_ICACHE_INTERFACE 0
C_ICACHE_VICTIMS 0
C_ICACHE_STREAMS 0
C_ICACHE_FORCE_TAG_LUTRAM 0
C_ICACHE_DATA_WIDTH 0
C_M_AXI_IC_SUPPORTS_THREADS 0
C_M_AXI_IC_THREAD_ID_WIDTH 1
C_M_AXI_IC_SUPPORTS_READ 1
C_M_AXI_IC_SUPPORTS_WRITE 0
C_M_AXI_IC_SUPPORTS_NARROW_BURST 0
C_M_AXI_IC_DATA_WIDTH 32
C_M_AXI_IC_ADDR_WIDTH 32
C_M_AXI_IC_PROTOCOL AXI4
C_M_AXI_IC_USER_VALUE 0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS 1
C_M_AXI_IC_AWUSER_WIDTH 5
C_M_AXI_IC_ARUSER_WIDTH 5
C_M_AXI_IC_WUSER_WIDTH 1
C_M_AXI_IC_RUSER_WIDTH 1
C_M_AXI_IC_BUSER_WIDTH 1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING 2
C_DCACHE_BASEADDR 0x00000000
C_DCACHE_HIGHADDR 0x3FFFFFFF
C_USE_DCACHE 0
C_ALLOW_DCACHE_WR 1
C_DCACHE_ADDR_TAG 17
C_DCACHE_BYTE_SIZE 8192
C_DCACHE_USE_FSL 1
C_DCACHE_LINE_LEN 4
C_DCACHE_ALWAYS_USED 0
C_DCACHE_INTERFACE 0
C_DCACHE_USE_WRITEBACK 0
C_DCACHE_VICTIMS 0
C_DCACHE_FORCE_TAG_LUTRAM 0
C_DCACHE_DATA_WIDTH 0
C_M_AXI_DC_SUPPORTS_THREADS 0
C_M_AXI_DC_THREAD_ID_WIDTH 1
C_M_AXI_DC_SUPPORTS_READ 1
C_M_AXI_DC_SUPPORTS_WRITE 1
C_M_AXI_DC_SUPPORTS_NARROW_BURST 0
C_M_AXI_DC_DATA_WIDTH 32
C_M_AXI_DC_ADDR_WIDTH 32
C_M_AXI_DC_PROTOCOL AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS 0
C_M_AXI_DC_USER_VALUE 0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS 1
C_M_AXI_DC_AWUSER_WIDTH 5
C_M_AXI_DC_ARUSER_WIDTH 5
C_M_AXI_DC_WUSER_WIDTH 1
C_M_AXI_DC_RUSER_WIDTH 1
C_M_AXI_DC_BUSER_WIDTH 1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING 2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING 32
C_USE_MMU 0
C_MMU_DTLB_SIZE 4
C_MMU_ITLB_SIZE 2
C_MMU_TLB_ACCESS 3
C_MMU_ZONES 16
C_MMU_PRIVILEGED_INSTR 0
C_USE_INTERRUPT 0
C_USE_EXT_BRK 0
C_USE_EXT_NM_BRK 0
C_USE_BRANCH_TARGET_CACHE 0
C_BRANCH_TARGET_CACHE_SIZE 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Debuggers TOP

debug_module   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

IP Specs
Core Version Documentation
mdm 2.00.b IP


debug_module IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Debug_SYS_Rst O 1 proc_sys_reset_0_MB_Debug_Sys_Rst
1 S_AXI_ACLK I 1 clk_100_0000MHz
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
MBDEBUG_0 INITIATOR XIL_MBDEBUG3 microblaze_0_debug microblaze_0
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_JTAG_CHAIN 2
C_INTERCONNECT 2
C_BASEADDR 0x41400000
C_HIGHADDR 0x4140FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 3
 
Name Value
C_SPLB_NUM_MASTERS 8
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_MB_DBG_PORTS 1
C_USE_UART 1
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Busses TOP

axi4lite_0   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.05.a IP


axi4lite_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 interconnect_aclk I 1 clk_100_0000MHz
1 INTERCONNECT_ARESETN I 1 proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER M_AXI_DP
microblaze_0 MASTER M_AXI_IP
debug_module SLAVE S_AXI
axi_uartlite_4 SLAVE S_AXI
Digilent_Shared_Mem_Bus_Mux SLAVE S_AXI
axi_uartlite_0 SLAVE S_AXI
axi_uartlite_1 SLAVE S_AXI
axi_uartlite_2 SLAVE S_AXI
axi_uartlite_3 SLAVE S_AXI
axi_gpio_0 SLAVE S_AXI
axi_gpio_1 SLAVE S_AXI
axi_gpio_2 SLAVE S_AXI
axi_gpio_3 SLAVE S_AXI
axi_gpio_4 SLAVE S_AXI
axi_gpio_5 SLAVE S_AXI
axi_gpio_6 SLAVE S_AXI
LEDS SLAVE S_AXI
axi2axi_connector_1 SLAVE S_AXI


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 32
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 0
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_interconnect_1   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.05.a IP


axi_interconnect_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 INTERCONNECT_ACLK I 1 clk_100_0000MHz
1 INTERCONNECT_ARESETN I 1 proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
axi2axi_connector_1 MASTER M_AXI
axi_iic_0 SLAVE S_AXI
axi_iic_1 SLAVE S_AXI
axi_iic_2 SLAVE S_AXI
axi_iic_3 SLAVE S_AXI
axi_spi_0 SLAVE S_AXI
axi_spi_1 SLAVE S_AXI
axi_spi_2 SLAVE S_AXI
axi_spi_3 SLAVE S_AXI


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 32
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 0
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


microblaze_0_dlmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 2.00.b IP


microblaze_0_dlmb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 SYS_RST I 1 proc_sys_reset_0_BUS_STRUCT_RESET
1 LMB_CLK I 1 clk_100_0000MHz
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER DLMB
microblaze_0_d_bram_ctrl SLAVE SLMB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_LMB_NUM_SLAVES 4
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_EXT_RESET_HIGH 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


microblaze_0_ilmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 2.00.b IP


microblaze_0_ilmb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 SYS_RST I 1 proc_sys_reset_0_BUS_STRUCT_RESET
1 LMB_CLK I 1 clk_100_0000MHz
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER ILMB
microblaze_0_i_bram_ctrl SLAVE SLMB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_LMB_NUM_SLAVES 4
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_EXT_RESET_HIGH 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Bridges TOP

axi2axi_connector_1   AXI to AXI Connector
Wire Bridge Between Two AXI Interconnects

IP Specs
Core Version Documentation
axi2axi_connector 1.00.a IP


axi2axi_connector_1 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXI MASTER AXI axi_interconnect_1 8 Peripherals.
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_ACLK_FREQ_HZ 100000000
C_S_AXI_ID_WIDTH 1
C_S_AXI_PROTOCOL AXI4
C_S_AXI_SUPPORTS_NARROW_BURST 1
C_S_AXI_SUPPORTS_READ 1
C_S_AXI_SUPPORTS_WRITE 1
C_S_AXI_SUPPORTS_USER_SIGNALS 0
C_S_AXI_AWUSER_WIDTH 1
C_S_AXI_ARUSER_WIDTH 1
C_S_AXI_WUSER_WIDTH 1
C_S_AXI_RUSER_WIDTH 1
C_S_AXI_BUSER_WIDTH 1
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE 8
C_M_AXI_ADDR_WIDTH 32
C_M_AXI_DATA_WIDTH 32
C_M_AXI_PROTOCOL AXI4
C_M_AXI_ACLK_FREQ_HZ 100000000
C_M_AXI_SUPPORTS_THREADS 1
C_M_AXI_THREAD_ID_WIDTH 1
C_M_AXI_SUPPORTS_NARROW_BURST 1
C_M_AXI_SUPPORTS_READ 1
C_M_AXI_SUPPORTS_WRITE 1
C_M_AXI_SUPPORTS_USER_SIGNALS 0
C_M_AXI_AWUSER_WIDTH 1
C_M_AXI_ARUSER_WIDTH 1
C_M_AXI_WUSER_WIDTH 1
C_M_AXI_RUSER_WIDTH 1
C_M_AXI_BUSER_WIDTH 1
C_INTERCONNECT_M_AXI_WRITE_ISSUING 8
C_INTERCONNECT_M_AXI_READ_ISSUING 8
C_S_AXI_NUM_ADDR_RANGES 8
C_S_AXI_RNG00_BASEADDR 0x40800000
C_S_AXI_RNG01_BASEADDR 0x40840000
 
Name Value
C_S_AXI_RNG02_BASEADDR 0x40880000
C_S_AXI_RNG03_BASEADDR 0x408C0000
C_S_AXI_RNG04_BASEADDR 0x40A00000
C_S_AXI_RNG05_BASEADDR 0x40A40000
C_S_AXI_RNG06_BASEADDR 0x40A80000
C_S_AXI_RNG07_BASEADDR 0x40AC0000
C_S_AXI_RNG08_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG09_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG10_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG11_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG12_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG13_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG14_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG15_BASEADDR 0xFFFFFFFF
C_S_AXI_RNG00_HIGHADDR 0x4080FFFF
C_S_AXI_RNG01_HIGHADDR 0x4084FFFF
C_S_AXI_RNG02_HIGHADDR 0x4088FFFF
C_S_AXI_RNG03_HIGHADDR 0x408CFFFF
C_S_AXI_RNG04_HIGHADDR 0x40A0FFFF
C_S_AXI_RNG05_HIGHADDR 0x40A4FFFF
C_S_AXI_RNG06_HIGHADDR 0x40A8FFFF
C_S_AXI_RNG07_HIGHADDR 0x40ACFFFF
C_S_AXI_RNG08_HIGHADDR 0x00000000
C_S_AXI_RNG09_HIGHADDR 0x00000000
C_S_AXI_RNG10_HIGHADDR 0x00000000
C_S_AXI_RNG11_HIGHADDR 0x00000000
C_S_AXI_RNG12_HIGHADDR 0x00000000
C_S_AXI_RNG13_HIGHADDR 0x00000000
C_S_AXI_RNG14_HIGHADDR 0x00000000
C_S_AXI_RNG15_HIGHADDR 0x00000000
C_INTERCONNECT_M_AXI_AW_REGISTER 7
C_INTERCONNECT_M_AXI_AR_REGISTER 7
C_INTERCONNECT_M_AXI_W_REGISTER 7
C_INTERCONNECT_M_AXI_R_REGISTER 7
C_INTERCONNECT_M_AXI_B_REGISTER 7
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memorys TOP

microblaze_0_bram_block   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


microblaze_0_bram_block IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block microblaze_0_i_bram_ctrl
PORTB TARGET XIL_BRAM microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block microblaze_0_d_bram_ctrl


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY virtex2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memory Controllers TOP

Digilent_Shared_Mem_Bus_Mux   Digilent Shared Memory Bus Multiplexer
Shared Memory Bus Multiplexer allows multiple memories to be used with the same address and data buses

IP Specs
Core Version Documentation
d_shared_mem_bus 1.00.a IP


Digilent_Shared_Mem_Bus_Mux IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 QSPI_Mem_S_O O 1 Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_S_O
2 Mem_OEN_O O 1 Digilent_Shared_Mem_Bus_Mux_Mem_OEN_O
3 Mem_WEN_O O 1 Digilent_Shared_Mem_Bus_Mux_Mem_WEN_O
4 QSPI_Mem_C_O O 1 Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_C_O
5 FLASH_Mem_CEN_O O 1 Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_CEN_O
6 FLASH_Mem_RPN_O O 1 Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_RPN_O
7 PSRAM_Mem_CEN_O O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CEN_O
8 PSRAM_Mem_ADV_O O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_ADV_O
9 PSRAM_Mem_CRE_O O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CRE_O
10 PSRAM_Mem_CLK_O O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CLK_O
11 PSRAM_Mem_Wait_I I 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_Wait_I
12 PSRAM_Mem_UB_O O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_UB_O
13 PSRAM_Mem_LB_O O 1 Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_LB_O
14 Mem_DQ IO 1 Digilent_Shared_Mem_Bus_Mux_Mem_DQ
15 Mem_Addr_O O 1 Digilent_Shared_Mem_Bus_Mux_Mem_Addr_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_PSRAM_RW_CYCLE_NS 100
C_FLASH_RD_CYCLE_NS 140
C_FLASH_WR_CYCLE_NS 60
C_QSPI_BASEADDR 0x72800000
C_QSPI_HIGHADDR 0x7280FFFF
C_PSRAM_BASEADDR 0x43000000
C_PSRAM_HIGHADDR 0x43FFFFFF
C_FLASH_BASEADDR 0x42000000
C_FLASH_HIGHADDR 0x42FFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


microblaze_0_d_bram_ctrl   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 3.00.b IP


microblaze_0_d_bram_ctrl IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
BRAM_PORT INITIATOR XIL_BRAM microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block microblaze_0_bram_block
SLMB SLAVE LMB microblaze_0_dlmb microblaze_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x00007FFF
C_FAMILY virtex5
C_MASK 0x00800000
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_ECC 0
C_INTERCONNECT 0
C_FAULT_INJECT 0
C_CE_FAILING_REGISTERS 0
C_UE_FAILING_REGISTERS 0
C_ECC_STATUS_REGISTERS 0
C_ECC_ONOFF_REGISTER 0
C_ECC_ONOFF_RESET_VALUE 1
C_CE_COUNTER_WIDTH 0
C_WRITE_ACCESS 2
 
Name Value
C_SPLB_CTRL_BASEADDR 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR 0x00000000
C_SPLB_CTRL_AWIDTH 32
C_SPLB_CTRL_DWIDTH 32
C_SPLB_CTRL_P2P 0
C_SPLB_CTRL_MID_WIDTH 1
C_SPLB_CTRL_NUM_MASTERS 1
C_SPLB_CTRL_SUPPORT_BURSTS 0
C_SPLB_CTRL_NATIVE_DWIDTH 32
C_SPLB_CTRL_CLK_FREQ_HZ 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ 100000000
C_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_S_AXI_CTRL_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


microblaze_0_i_bram_ctrl   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 3.00.b IP


microblaze_0_i_bram_ctrl IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
BRAM_PORT INITIATOR XIL_BRAM microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block microblaze_0_bram_block
SLMB SLAVE LMB microblaze_0_ilmb microblaze_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x00007FFF
C_FAMILY virtex5
C_MASK 0x00800000
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_ECC 0
C_INTERCONNECT 0
C_FAULT_INJECT 0
C_CE_FAILING_REGISTERS 0
C_UE_FAILING_REGISTERS 0
C_ECC_STATUS_REGISTERS 0
C_ECC_ONOFF_REGISTER 0
C_ECC_ONOFF_RESET_VALUE 1
C_CE_COUNTER_WIDTH 0
C_WRITE_ACCESS 2
 
Name Value
C_SPLB_CTRL_BASEADDR 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR 0x00000000
C_SPLB_CTRL_AWIDTH 32
C_SPLB_CTRL_DWIDTH 32
C_SPLB_CTRL_P2P 0
C_SPLB_CTRL_MID_WIDTH 1
C_SPLB_CTRL_NUM_MASTERS 1
C_SPLB_CTRL_SUPPORT_BURSTS 0
C_SPLB_CTRL_NATIVE_DWIDTH 32
C_SPLB_CTRL_CLK_FREQ_HZ 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ 100000000
C_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_S_AXI_CTRL_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Peripherals TOP

LEDS   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


LEDS IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 GPIO_IO_O O 1 LEDS_GPIO_IO_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x401C0000
C_HIGHADDR 0x401CFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_0   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 GPIO_IO_O O 1 axi_gpio_0_GPIO_IO_O
2 GPIO_IO_T O 1 axi_gpio_0_GPIO_IO_T
3 GPIO_IO_I I 1 axi_gpio_0_GPIO_IO_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40000000
C_HIGHADDR 0x4000FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_1   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 GPIO_IO_I I 1 axi_gpio_1_GPIO_IO_I
2 GPIO_IO_T O 1 axi_gpio_1_GPIO_IO_T
3 GPIO_IO_O O 1 axi_gpio_1_GPIO_IO_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40040000
C_HIGHADDR 0x4004FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_2   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 GPIO_IO_I I 1 axi_gpio_2_GPIO_IO_I
2 GPIO_IO_O O 1 axi_gpio_2_GPIO_IO_O
3 GPIO_IO_T O 1 axi_gpio_2_GPIO_IO_T
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40080000
C_HIGHADDR 0x4008FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_3   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_3 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 GPIO_IO_T O 1 axi_gpio_3_GPIO_IO_T
2 GPIO_IO_O O 1 axi_gpio_3_GPIO_IO_O
3 GPIO_IO_I I 1 axi_gpio_3_GPIO_IO_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x400C0000
C_HIGHADDR 0x400CFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_4   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_4 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 GPIO_IO_O O 1 axi_gpio_4_GPIO_IO_O
2 GPIO_IO_I I 1 axi_gpio_4_GPIO_IO_I
3 GPIO_IO_T O 1 axi_gpio_4_GPIO_IO_T
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40100000
C_HIGHADDR 0x4010FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_5   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_5 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 GPIO_IO_O O 1 axi_gpio_5_GPIO_IO_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40140000
C_HIGHADDR 0x4014FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 32
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_6   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_6 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 GPIO_IO_I I 1 net_axi_gpio_6_GPIO_IO_I_pin
2 GPIO_IO_O O 1 axi_gpio_6_GPIO_IO_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40180000
C_HIGHADDR 0x4018FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 32
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_iic_0   AXI IIC Interface
AXI interface to Philips I2C bus v2.1

IP Specs
Core Version Documentation
axi_iic 1.01.b IP


axi_iic_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 Scl_I I 1 axi_iic_0_Scl_I
2 Scl_T O 1 axi_iic_0_Scl_T
3 Sda_T O 1 axi_iic_0_Sda_T
4 Scl_O O 1 axi_iic_0_Scl_O
5 Sda_O O 1 axi_iic_0_Sda_O
6 Sda_I I 1 axi_iic_0_Sda_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 8 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40800000
C_HIGHADDR 0x4080FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_IIC_FREQ 100000
C_TEN_BIT_ADR 0
 
Name Value
C_GPO_WIDTH 1
C_S_AXI_ACLK_FREQ_HZ 25000000
C_SCL_INERTIAL_DELAY 0
C_SDA_INERTIAL_DELAY 0
C_SDA_LEVEL 1
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_iic_1   AXI IIC Interface
AXI interface to Philips I2C bus v2.1

IP Specs
Core Version Documentation
axi_iic 1.01.b IP


axi_iic_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 Sda_T O 1 axi_iic_1_Sda_T
2 Scl_T O 1 axi_iic_1_Scl_T
3 Sda_O O 1 axi_iic_1_Sda_O
4 Scl_O O 1 axi_iic_1_Scl_O
5 Scl_I I 1 axi_iic_1_Scl_I
6 Sda_I I 1 axi_iic_1_Sda_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 8 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40840000
C_HIGHADDR 0x4084FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_IIC_FREQ 100000
C_TEN_BIT_ADR 0
 
Name Value
C_GPO_WIDTH 1
C_S_AXI_ACLK_FREQ_HZ 25000000
C_SCL_INERTIAL_DELAY 0
C_SDA_INERTIAL_DELAY 0
C_SDA_LEVEL 1
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_iic_2   AXI IIC Interface
AXI interface to Philips I2C bus v2.1

IP Specs
Core Version Documentation
axi_iic 1.01.b IP


axi_iic_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 Scl_O O 1 axi_iic_2_Scl_O
2 Scl_I I 1 axi_iic_2_Scl_I
3 Sda_O O 1 axi_iic_2_Sda_O
4 Sda_T O 1 axi_iic_2_Sda_T
5 Scl_T O 1 axi_iic_2_Scl_T
6 Sda_I I 1 axi_iic_2_Sda_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 8 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40880000
C_HIGHADDR 0x4088FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_IIC_FREQ 100000
C_TEN_BIT_ADR 0
 
Name Value
C_GPO_WIDTH 1
C_S_AXI_ACLK_FREQ_HZ 25000000
C_SCL_INERTIAL_DELAY 0
C_SDA_INERTIAL_DELAY 0
C_SDA_LEVEL 1
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_iic_3   AXI IIC Interface
AXI interface to Philips I2C bus v2.1

IP Specs
Core Version Documentation
axi_iic 1.01.b IP


axi_iic_3 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 Scl_I I 1 axi_iic_3_Scl_I
2 Sda_O O 1 axi_iic_3_Sda_O
3 Scl_O O 1 axi_iic_3_Scl_O
4 Sda_T O 1 axi_iic_3_Sda_T
5 Scl_T O 1 axi_iic_3_Scl_T
6 Sda_I I 1 axi_iic_3_Sda_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 8 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x408C0000
C_HIGHADDR 0x408CFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_IIC_FREQ 100000
C_TEN_BIT_ADR 0
 
Name Value
C_GPO_WIDTH 1
C_S_AXI_ACLK_FREQ_HZ 25000000
C_SCL_INERTIAL_DELAY 0
C_SDA_INERTIAL_DELAY 0
C_SDA_LEVEL 1
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_spi_0   AXI SPI Interface
AXI to Motorola Serial Peripheral Interface (SPI) adapter

IP Specs
Core Version Documentation
axi_spi 1.02.a IP


axi_spi_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 SPISEL I 1 axi_spi_0_SPISEL
2 SS_O O 1 axi_spi_0_SS_O
3 SCK_O O 1 axi_spi_0_SCK_O
4 MOSI_O O 1 axi_spi_0_MOSI_O
5 MISO_I I 1 axi_spi_0_MISO_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 8 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40A00000
C_HIGHADDR 0x40A0FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_FIFO_EXIST 1
C_SCK_RATIO 32
C_NUM_SS_BITS 1
C_NUM_TRANSFER_BITS 8
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_spi_1   AXI SPI Interface
AXI to Motorola Serial Peripheral Interface (SPI) adapter

IP Specs
Core Version Documentation
axi_spi 1.02.a IP


axi_spi_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 SPISEL I 1 axi_spi_1_SPISEL
2 SS_O O 1 axi_spi_1_SS_O
3 SCK_O O 1 axi_spi_1_SCK_O
4 MISO_I I 1 axi_spi_1_MISO_I
5 MOSI_O O 1 axi_spi_1_MOSI_O
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 8 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40A40000
C_HIGHADDR 0x40A4FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_FIFO_EXIST 1
C_SCK_RATIO 32
C_NUM_SS_BITS 1
C_NUM_TRANSFER_BITS 8
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_spi_2   AXI SPI Interface
AXI to Motorola Serial Peripheral Interface (SPI) adapter

IP Specs
Core Version Documentation
axi_spi 1.02.a IP


axi_spi_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 SPISEL I 1 axi_spi_2_SPISEL
2 SS_O O 1 axi_spi_2_SS_O
3 SCK_O O 1 axi_spi_2_SCK_O
4 MOSI_O O 1 axi_spi_2_MOSI_O
5 MISO_I I 1 axi_spi_2_MISO_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 8 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40A80000
C_HIGHADDR 0x40A8FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_FIFO_EXIST 1
C_SCK_RATIO 32
C_NUM_SS_BITS 1
C_NUM_TRANSFER_BITS 8
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_spi_3   AXI SPI Interface
AXI to Motorola Serial Peripheral Interface (SPI) adapter

IP Specs
Core Version Documentation
axi_spi 1.02.a IP


axi_spi_3 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 SPISEL I 1 axi_spi_3_SPISEL
2 SS_O O 1 axi_spi_3_SS_O
3 SCK_O O 1 axi_spi_3_SCK_O
4 MOSI_O O 1 axi_spi_3_MOSI_O
5 MISO_I I 1 axi_spi_3_MISO_I
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi_interconnect_1 8 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x40AC0000
C_HIGHADDR 0x40ACFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_FIFO_EXIST 1
C_SCK_RATIO 32
C_NUM_SS_BITS 1
C_NUM_TRANSFER_BITS 8
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uartlite_0   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uartlite_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 RX I 1 axi_uartlite_0_RX
2 TX O 1 axi_uartlite_0_TX
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x40640000
C_HIGHADDR 0x4064FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
 
Name Value
C_BAUDRATE 9600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uartlite_1   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uartlite_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 RX I 1 axi_uartlite_1_RX
2 TX O 1 axi_uartlite_1_TX
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x40680000
C_HIGHADDR 0x4068FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
 
Name Value
C_BAUDRATE 9600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uartlite_2   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uartlite_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 RX I 1 axi_uartlite_2_RX
2 TX O 1 axi_uartlite_2_TX
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x406C0000
C_HIGHADDR 0x406CFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
 
Name Value
C_BAUDRATE 9600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uartlite_3   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uartlite_3 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 RX I 1 axi_uartlite_3_RX
2 TX O 1 axi_uartlite_3_TX
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x40700000
C_HIGHADDR 0x4070FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
 
Name Value
C_BAUDRATE 9600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uartlite_4   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uartlite_4 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 TX O 1 RS232_Uart_1_sout
2 RX I 1 RS232_Uart_1_sin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 16 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x40600000
C_HIGHADDR 0x4060FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
 
Name Value
C_BAUDRATE 115200
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 1
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




IP TOP

clock_generator_0   Clock Generator
Clock generator for processor system.

IP Specs
Core Version Documentation
clock_generator 4.03.a IP


clock_generator_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 LOCKED O 1 proc_sys_reset_0_Dcm_locked
1 CLKOUT0 O 1 clk_100_0000MHz
2 RST I 1 RESET
3 CLKIN I 1 GCLK


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_DEVICE NOT_SET
C_PACKAGE NOT_SET
C_SPEEDGRADE NOT_SET
C_CLKIN_FREQ 100000000
C_CLKOUT0_FREQ 100000000
C_CLKOUT0_PHASE 0
C_CLKOUT0_GROUP NONE
C_CLKOUT0_BUF TRUE
C_CLKOUT0_VARIABLE_PHASE FALSE
C_CLKOUT1_FREQ 0
C_CLKOUT1_PHASE 0
C_CLKOUT1_GROUP NONE
C_CLKOUT1_BUF TRUE
C_CLKOUT1_VARIABLE_PHASE FALSE
C_CLKOUT2_FREQ 0
C_CLKOUT2_PHASE 0
C_CLKOUT2_GROUP NONE
C_CLKOUT2_BUF TRUE
C_CLKOUT2_VARIABLE_PHASE FALSE
C_CLKOUT3_FREQ 0
C_CLKOUT3_PHASE 0
C_CLKOUT3_GROUP NONE
C_CLKOUT3_BUF TRUE
C_CLKOUT3_VARIABLE_PHASE FALSE
C_CLKOUT4_FREQ 0
C_CLKOUT4_PHASE 0
C_CLKOUT4_GROUP NONE
C_CLKOUT4_BUF TRUE
C_CLKOUT4_VARIABLE_PHASE FALSE
C_CLKOUT5_FREQ 0
C_CLKOUT5_PHASE 0
C_CLKOUT5_GROUP NONE
C_CLKOUT5_BUF TRUE
C_CLKOUT5_VARIABLE_PHASE FALSE
C_CLKOUT6_FREQ 0
C_CLKOUT6_PHASE 0
C_CLKOUT6_GROUP NONE
C_CLKOUT6_BUF TRUE
C_CLKOUT6_VARIABLE_PHASE FALSE
C_CLKOUT7_FREQ 0
C_CLKOUT7_PHASE 0
C_CLKOUT7_GROUP NONE
C_CLKOUT7_BUF TRUE
C_CLKOUT7_VARIABLE_PHASE FALSE
C_CLKOUT8_FREQ 0
C_CLKOUT8_PHASE 0
C_CLKOUT8_GROUP NONE
C_CLKOUT8_BUF TRUE
C_CLKOUT8_VARIABLE_PHASE FALSE
C_CLKOUT9_FREQ 0
C_CLKOUT9_PHASE 0
C_CLKOUT9_GROUP NONE
C_CLKOUT9_BUF TRUE
C_CLKOUT9_VARIABLE_PHASE FALSE
C_CLKOUT10_FREQ 0
 
Name Value
C_CLKOUT10_PHASE 0
C_CLKOUT10_GROUP NONE
C_CLKOUT10_BUF TRUE
C_CLKOUT10_VARIABLE_PHASE FALSE
C_CLKOUT11_FREQ 0
C_CLKOUT11_PHASE 0
C_CLKOUT11_GROUP NONE
C_CLKOUT11_BUF TRUE
C_CLKOUT11_VARIABLE_PHASE FALSE
C_CLKOUT12_FREQ 0
C_CLKOUT12_PHASE 0
C_CLKOUT12_GROUP NONE
C_CLKOUT12_BUF TRUE
C_CLKOUT12_VARIABLE_PHASE FALSE
C_CLKOUT13_FREQ 0
C_CLKOUT13_PHASE 0
C_CLKOUT13_GROUP NONE
C_CLKOUT13_BUF TRUE
C_CLKOUT13_VARIABLE_PHASE FALSE
C_CLKOUT14_FREQ 0
C_CLKOUT14_PHASE 0
C_CLKOUT14_GROUP NONE
C_CLKOUT14_BUF TRUE
C_CLKOUT14_VARIABLE_PHASE FALSE
C_CLKOUT15_FREQ 0
C_CLKOUT15_PHASE 0
C_CLKOUT15_GROUP NONE
C_CLKOUT15_BUF TRUE
C_CLKOUT15_VARIABLE_PHASE FALSE
C_CLKFBIN_FREQ 0
C_CLKFBIN_DESKEW NONE
C_CLKFBOUT_FREQ 0
C_CLKFBOUT_PHASE 0
C_CLKFBOUT_GROUP NONE
C_CLKFBOUT_BUF TRUE
C_PSDONE_GROUP NONE
C_EXT_RESET_HIGH 1
C_CLK_PRIMITIVE_FEEDBACK_BUF FALSE
C_CLKOUT0_DUTY_CYCLE 0.500000
C_CLKOUT1_DUTY_CYCLE 0.500000
C_CLKOUT2_DUTY_CYCLE 0.500000
C_CLKOUT3_DUTY_CYCLE 0.500000
C_CLKOUT4_DUTY_CYCLE 0.500000
C_CLKOUT5_DUTY_CYCLE 0.500000
C_CLKOUT6_DUTY_CYCLE 0.500000
C_CLKOUT7_DUTY_CYCLE 0.500000
C_CLKOUT8_DUTY_CYCLE 0.500000
C_CLKOUT9_DUTY_CYCLE 0.500000
C_CLKOUT10_DUTY_CYCLE 0.500000
C_CLKOUT11_DUTY_CYCLE 0.500000
C_CLKOUT12_DUTY_CYCLE 0.500000
C_CLKOUT13_DUTY_CYCLE 0.500000
C_CLKOUT14_DUTY_CYCLE 0.500000
C_CLKOUT15_DUTY_CYCLE 0.500000
C_CLK_GEN UPDATE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


proc_sys_reset_0   Processor System Reset Module
Reset management module

IP Specs
Core Version Documentation
proc_sys_reset 3.00.a IP


proc_sys_reset_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MB_Debug_Sys_Rst I 1 proc_sys_reset_0_MB_Debug_Sys_Rst
1 Dcm_locked I 1 proc_sys_reset_0_Dcm_locked
2 MB_Reset O 1 proc_sys_reset_0_MB_Reset
3 Slowest_sync_clk I 1 clk_100_0000MHz
4 Interconnect_aresetn O 1 proc_sys_reset_0_Interconnect_aresetn
5 Ext_Reset_In I 1 RESET
6 BUS_STRUCT_RESET O 1 proc_sys_reset_0_BUS_STRUCT_RESET


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SUBFAMILY lx
C_EXT_RST_WIDTH 4
C_AUX_RST_WIDTH 4
C_EXT_RESET_HIGH 1
C_AUX_RESET_HIGH 1
C_NUM_BUS_RST 1
C_NUM_PERP_RST 1
C_NUM_INTERCONNECT_ARESETN 1
C_NUM_PERP_ARESETN 1
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Timing Information TOP


Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.