top Project Status (03/11/2012 - 15:01:01)
Project File: top.xise Parser Errors: No Errors
Module Name: top Implementation State: Programming File Not Generated (Stopped)
Target Device: xc6slx16-2csg324
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
 
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log FileSun Mar 11 14:37:15 201209 Warnings (1 new)19 Infos (0 new)
Simgen Log File    
BitInit Log FileSun Mar 11 14:19:25 2012009 Infos (0 new)
System Log File    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentSun Mar 11 14:57:56 2012
WebTalk Log FileOut of DateSun Mar 11 14:19:17 2012

Date Generated: 03/11/2012 - 15:01:01