Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
5,513 |
18,224 |
30% |
|
Number used as Flip Flops |
5,440 |
|
|
|
Number used as Latches |
68 |
|
|
|
Number used as Latch-thrus |
0 |
|
|
|
Number used as AND/OR logics |
5 |
|
|
|
Number of Slice LUTs |
7,263 |
9,112 |
79% |
|
Number used as logic |
6,841 |
9,112 |
75% |
|
Number using O6 output only |
5,357 |
|
|
|
Number using O5 output only |
111 |
|
|
|
Number using O5 and O6 |
1,373 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
313 |
2,176 |
14% |
|
Number used as Dual Port RAM |
64 |
|
|
|
Number using O6 output only |
0 |
|
|
|
Number using O5 output only |
0 |
|
|
|
Number using O5 and O6 |
64 |
|
|
|
Number used as Single Port RAM |
0 |
|
|
|
Number used as Shift Register |
249 |
|
|
|
Number using O6 output only |
40 |
|
|
|
Number using O5 output only |
1 |
|
|
|
Number using O5 and O6 |
208 |
|
|
|
Number used exclusively as route-thrus |
109 |
|
|
|
Number with same-slice register load |
79 |
|
|
|
Number with same-slice carry load |
29 |
|
|
|
Number with other load |
1 |
|
|
|
Number of occupied Slices |
2,274 |
2,278 |
99% |
|
Nummber of MUXCYs used |
1,020 |
4,556 |
22% |
|
Number of LUT Flip Flop pairs used |
7,729 |
|
|
|
Number with an unused Flip Flop |
2,789 |
7,729 |
36% |
|
Number with an unused LUT |
466 |
7,729 |
6% |
|
Number of fully used LUT-FF pairs |
4,474 |
7,729 |
57% |
|
Number of unique control sets |
450 |
|
|
|
Number of slice register sites lost to control set restrictions |
1,603 |
18,224 |
8% |
|
Number of bonded IOBs |
110 |
232 |
47% |
|
Number of LOCed IOBs |
110 |
110 |
100% |
|
IOB Flip Flops |
4 |
|
|
|
Number of RAMB16BWERs |
16 |
32 |
50% |
|
Number of RAMB8BWERs |
2 |
64 |
3% |
|
Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
Number used as BUFIO2s |
1 |
|
|
|
Number used as BUFIO2_2CLKs |
0 |
|
|
|
Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
Number of BUFG/BUFGMUXs |
6 |
16 |
37% |
|
Number used as BUFGs |
6 |
|
|
|
Number used as BUFGMUX |
0 |
|
|
|
Number of DCM/DCM_CLKGENs |
1 |
4 |
25% |
|
Number used as DCMs |
1 |
|
|
|
Number used as DCM_CLKGENs |
0 |
|
|
|
Number of ILOGIC2/ISERDES2s |
4 |
248 |
1% |
|
Number used as ILOGIC2s |
4 |
|
|
|
Number used as ISERDES2s |
0 |
|
|
|
Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
248 |
0% |
|
Number of OLOGIC2/OSERDES2s |
0 |
248 |
0% |
|
Number of BSCANs |
1 |
4 |
25% |
|
Number of BUFHs |
0 |
128 |
0% |
|
Number of BUFPLLs |
0 |
8 |
0% |
|
Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
Number of DSP48A1s |
3 |
32 |
9% |
|
Number of ICAPs |
0 |
1 |
0% |
|
Number of MCBs |
0 |
2 |
0% |
|
Number of PCILOGICSEs |
0 |
2 |
0% |
|
Number of PLL_ADVs |
1 |
2 |
50% |
|
Number of PMVs |
0 |
1 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
Average Fanout of Non-Clock Nets |
4.13 |
|
|
|