top Project Status (03/11/2012 - 15:01:01) | |||
Project File: | top.xise | Parser Errors: | No Errors |
Module Name: | top | Implementation State: | Programming File Not Generated (Stopped) |
Target Device: | xc6slx16-2csg324 |
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Product Version: | ISE 13.4 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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XPS Reports | [-] | ||||
Report Name | Generated | Errors | Warnings | Infos | |
Platgen Log File | Sun Mar 11 14:37:15 2012 | 0 | 9 Warnings (1 new) | 19 Infos (0 new) | |
Simgen Log File | |||||
BitInit Log File | Sun Mar 11 14:19:25 2012 | 0 | 0 | 9 Infos (0 new) | |
System Log File |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Sun Mar 11 14:57:56 2012 | |
WebTalk Log File | Out of Date | Sun Mar 11 14:19:17 2012 |